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[FMV][AArch64] Remove feature sha1 from FMV. #108383

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Merged
merged 7 commits into from
Sep 27, 2024
Merged

[FMV][AArch64] Remove feature sha1 from FMV. #108383

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50820f4
[FMV][AArch64] Remove feature sha1 from FMV.
labrinea Sep 12, 2024
3fb81b4
Merge branch 'main' into fmv-remove-sha1
labrinea Sep 19, 2024
6c0485d
Changes from last revision:
labrinea Sep 19, 2024
d5e1b18
Merge branch 'main' into fmv-remove-sha1
labrinea Sep 20, 2024
c706082
Merge branch 'main' into fmv-remove-sha1
labrinea Sep 27, 2024
b1d4397
Merge branch 'main' into fmv-remove-sha1
labrinea Sep 27, 2024
927b913
Merge branch 'main' into fmv-remove-sha1
labrinea Sep 27, 2024
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12 changes: 6 additions & 6 deletions clang/test/CodeGen/aarch64-cpu-supports.c
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Original file line number Diff line number Diff line change
Expand Up @@ -8,26 +8,26 @@
// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 70368744177664
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 70368744177664
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 35184372088832
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 35184372088832
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
// CHECK-NEXT: br i1 [[TMP3]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
// CHECK: if.then:
// CHECK-NEXT: store i32 1, ptr [[RETVAL]], align 4
// CHECK-NEXT: br label [[RETURN:%.*]]
// CHECK: if.end:
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 9070970929152
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 9070970929152
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4535485464576
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 4535485464576
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
// CHECK-NEXT: br i1 [[TMP7]], label [[IF_THEN1:%.*]], label [[IF_END2:%.*]]
// CHECK: if.then1:
// CHECK-NEXT: store i32 2, ptr [[RETVAL]], align 4
// CHECK-NEXT: br label [[RETURN]]
// CHECK: if.end2:
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 166633186212708352
// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 166633186212708352
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 83316593106354176
// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 83316593106354176
// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]]
// CHECK-NEXT: br i1 [[TMP11]], label [[IF_THEN3:%.*]], label [[IF_END4:%.*]]
// CHECK: if.then3:
Expand Down
3 changes: 0 additions & 3 deletions clang/test/CodeGen/aarch64-fmv-dependencies.c
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Expand Up @@ -117,9 +117,6 @@ __attribute__((target_version("rpres"))) int fmv(void) { return 0; }
// CHECK: define dso_local i32 @fmv._Msb() #[[sb:[0-9]+]] {
__attribute__((target_version("sb"))) int fmv(void) { return 0; }

// CHECK: define dso_local i32 @fmv._Msha1() #[[ATTR0:[0-9]+]] {
__attribute__((target_version("sha1"))) int fmv(void) { return 0; }

// CHECK: define dso_local i32 @fmv._Msha2() #[[sha2:[0-9]+]] {
__attribute__((target_version("sha2"))) int fmv(void) { return 0; }

Expand Down
12 changes: 6 additions & 6 deletions clang/test/CodeGen/aarch64-mixed-target-attributes.c
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Original file line number Diff line number Diff line change
Expand Up @@ -66,8 +66,8 @@ __attribute__((target_version("jscvt"))) int default_def_with_version_decls(void
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_cpu_features_resolver()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1048576
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1048576
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 524288
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 524288
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
Expand Down Expand Up @@ -140,8 +140,8 @@ __attribute__((target_version("jscvt"))) int default_def_with_version_decls(void
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_cpu_features_resolver()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1048576
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1048576
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 524288
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 524288
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
Expand Down Expand Up @@ -207,8 +207,8 @@ __attribute__((target_version("jscvt"))) int default_def_with_version_decls(void
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_cpu_features_resolver()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1048576
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1048576
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 524288
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 524288
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
Expand Down
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