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[TTI][RISCV] Unconditionally break critical edges to sink ADDI #108889

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Merged
merged 8 commits into from
Nov 26, 2024
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[TTI][RISCV] Unconditionally break critical edges to sink ADDI #108889

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[TTI][RISCV] Unconditionally break critical edges to sink ADDI
preames Sep 16, 2024
4c878bb
Start fixing failed rebase
preames Sep 16, 2024
aeec393
test convert
preames Sep 16, 2024
4a89449
Address review comment
preames Sep 17, 2024
5fa0835
Merge branch 'main' into pr-riscv-machine-sink-addi
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Clang format
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Merge branch 'main' into pr-riscv-machine-sink-addi
preames Nov 25, 2024
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Merge branch 'main' into pr-riscv-machine-sink-addi
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6 changes: 6 additions & 0 deletions llvm/include/llvm/CodeGen/TargetInstrInfo.h
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Expand Up @@ -159,6 +159,12 @@ class TargetInstrInfo : public MCInstrInfo {
return true;
}

/// For a "cheap" instruction which doesn't enable additional sinking,
/// should MachineSink break a critical edge to sink it anyways?
virtual bool shouldBreakCriticalEdgeToSink(MachineInstr &MI) const {
return false;
}

protected:
/// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
/// set, this hook lets the target specify whether the instruction is actually
Expand Down
4 changes: 3 additions & 1 deletion llvm/lib/CodeGen/MachineSink.cpp
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Expand Up @@ -952,7 +952,9 @@ bool MachineSinking::isWorthBreakingCriticalEdge(
}
}

return false;
// Let the target decide if it's worth breaking this
// critical edge for a "cheap" instruction.
return TII->shouldBreakCriticalEdgeToSink(MI);
}

bool MachineSinking::isLegalToBreakCriticalEdge(MachineInstr &MI,
Expand Down
5 changes: 5 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.h
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Expand Up @@ -78,6 +78,11 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {

bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;

bool shouldBreakCriticalEdgeToSink(MachineInstr &MI) const override {
return MI.getOpcode() == RISCV::ADDI && MI.getOperand(1).isReg() &&
MI.getOperand(1).getReg() == RISCV::X0;
}

void copyPhysRegVector(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
MCRegister DstReg, MCRegister SrcReg, bool KillSrc,
Expand Down
14 changes: 8 additions & 6 deletions llvm/test/CodeGen/RISCV/aext-to-sext.ll
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Expand Up @@ -78,12 +78,14 @@ bar:
define i64 @sext_phi_constants(i32 signext %c) {
; RV64I-LABEL: sext_phi_constants:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, -1
; RV64I-NEXT: bnez a0, .LBB2_2
; RV64I-NEXT: # %bb.1: # %iffalse
; RV64I-NEXT: li a1, -2
; RV64I-NEXT: .LBB2_2: # %merge
; RV64I-NEXT: slli a0, a1, 32
; RV64I-NEXT: beqz a0, .LBB2_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: li a0, -1
; RV64I-NEXT: j .LBB2_3
; RV64I-NEXT: .LBB2_2: # %iffalse
; RV64I-NEXT: li a0, -2
; RV64I-NEXT: .LBB2_3: # %merge
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ret
%a = icmp ne i32 %c, 0
Expand Down
84 changes: 40 additions & 44 deletions llvm/test/CodeGen/RISCV/compress-opt-select.ll
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Expand Up @@ -3,43 +3,39 @@
; The optimization should appear only with +c, otherwise default isel should be
; choosen.
;
; RUN: cat %s | sed 's/CMPCOND/eq/g' | sed 's/RESBRNORMAL/beq/g' | \
; RUN: sed 's/RESBROPT/c.beqz/g' > %t.compress_eq
; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c,+f,+d -filetype=obj \
; RUN: -disable-block-placement < %t.compress_eq \
; RUN: cat %s | sed 's/CMPCOND/eq/g' \
; RUN: | llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c,+f,+d \
; RUN: -filetype=obj -disable-block-placement \
; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \
; RUN: | FileCheck -check-prefix=RV32IFDC %t.compress_eq
; RUN: | FileCheck -check-prefix=RV32IFDC %s
;
; RUN: cat %s | sed -e 's/CMPCOND/eq/g' | sed -e 's/RESBRNORMAL/beq/g'\
; RUN: | sed -e 's/RESBROPT/c.beqz/g' > %t.nocompr_eq
; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=-c,+f,+d -filetype=obj \
; RUN: -disable-block-placement < %t.nocompr_eq \
; RUN: cat %s | sed -e 's/CMPCOND/eq/g' \
; RUN: | llc -mtriple=riscv32 -target-abi ilp32d -mattr=-c,+f,+d \
; RUN: -filetype=obj -disable-block-placement \
; RUN: | llvm-objdump -d --triple=riscv32 --mattr=-c,+f,+d -M no-aliases - \
; RUN: | FileCheck -check-prefix=RV32IFD %t.nocompr_eq
; RUN: | FileCheck -check-prefix=RV32IFD %s
;
; RUN: cat %s | sed 's/CMPCOND/ne/g' | sed 's/RESBRNORMAL/bne/g' | \
; RUN: sed 's/RESBROPT/c.bnez/g' > %t.compress_neq
; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c,+f,+d -filetype=obj \
; RUN: -disable-block-placement < %t.compress_neq \
; RUN: cat %s | sed 's/CMPCOND/ne/g' \
; RUN: | llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c,+f,+d \
; RUN: -filetype=obj -disable-block-placement \
; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \
; RUN: | FileCheck -check-prefix=RV32IFDC %t.compress_neq
; RUN: | FileCheck -check-prefix=RV32IFDC %s
;
; RUN: cat %s | sed -e 's/CMPCOND/ne/g' | sed -e 's/RESBRNORMAL/bne/g'\
; RUN: | sed -e 's/RESBROPT/c.bnez/g' > %t.nocompr_neq
; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=-c,+f,+d -filetype=obj \
; RUN: -disable-block-placement < %t.nocompr_neq \
; RUN: cat %s | sed -e 's/CMPCOND/ne/g' \
; RUN: | llc -mtriple=riscv32 -target-abi ilp32d -mattr=-c,+f,+d \
; RUN: -filetype=obj -disable-block-placement \
; RUN: | llvm-objdump -d --triple=riscv32 --mattr=-c,+f,+d -M no-aliases - \
; RUN: | FileCheck -check-prefix=RV32IFD %t.nocompr_neq
; RUN: | FileCheck -check-prefix=RV32IFD %s


; constant is small and fit in 6 bit (compress imm)
; RV32IFDC-LABEL: <f_small_pos>:
; RV32IFDC: c.li [[REG:.*]], 0x14
; RV32IFDC: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
; RV32IFDC: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
; --- no compress extension
; RV32IFD-LABEL: <f_small_pos>:
; RV32IFD: addi [[REG:.*]], zero, 0x14
; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @f_small_pos(i32 %in0) minsize {
%cmp = icmp CMPCOND i32 %in0, 20
%toRet = select i1 %cmp, i32 -99, i32 42
Expand All @@ -49,11 +45,11 @@ define i32 @f_small_pos(i32 %in0) minsize {
; constant is small and fit in 6 bit (compress imm)
; RV32IFDC-LABEL: <f_small_neg>:
; RV32IFDC: c.li [[REG:.*]], -0x14
; RV32IFDC: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
; RV32IFDC: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
; --- no compress extension
; RV32IFD-LABEL: <f_small_neg>:
; RV32IFD: addi [[REG:.*]], zero, -0x14
; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @f_small_neg(i32 %in0) minsize {
%cmp = icmp CMPCOND i32 %in0, -20
%toRet = select i1 %cmp, i32 -99, i32 42
Expand All @@ -63,11 +59,11 @@ define i32 @f_small_neg(i32 %in0) minsize {
; constant is small and fit in 6 bit (compress imm)
; RV32IFDC-LABEL: <f_small_edge_pos>:
; RV32IFDC: c.li [[REG:.*]], 0x1f
; RV32IFDC: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
; RV32IFDC: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
; --- no compress extension
; RV32IFD-LABEL: <f_small_edge_pos>:
; RV32IFD: addi [[REG:.*]], zero, 0x1f
; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @f_small_edge_pos(i32 %in0) minsize {
%cmp = icmp CMPCOND i32 %in0, 31
%toRet = select i1 %cmp, i32 -99, i32 42
Expand All @@ -77,11 +73,11 @@ define i32 @f_small_edge_pos(i32 %in0) minsize {
; constant is small and fit in 6 bit (compress imm)
; RV32IFDC-LABEL: <f_small_edge_neg>:
; RV32IFDC: c.li [[REG:.*]], -0x20
; RV32IFDC: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
; RV32IFDC: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
; --- no compress extension
; RV32IFD-LABEL: <f_small_edge_neg>:
; RV32IFD: addi [[REG:.*]], zero, -0x20
; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @f_small_edge_neg(i32 %in0) minsize {
%cmp = icmp CMPCOND i32 %in0, -32
%toRet = select i1 %cmp, i32 -99, i32 42
Expand All @@ -91,14 +87,14 @@ define i32 @f_small_edge_neg(i32 %in0) minsize {
; constant is medium and not fit in 6 bit (compress imm),
; but fit in 12 bit (imm)
; RV32IFDC-LABEL: <f_medium_ledge_pos>:
; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], -0x20
; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]]
; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], -0x21
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@topperc topperc Sep 17, 2024

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Is REG here zero like in the RV32IFD case?

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@topperc topperc Sep 17, 2024

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Nevermind. It's not.

; RV32IFDC: [[COND:c.b.*]] [[MAYZEROREG]], [[PLACE:.*]]
; --- no compress extension
; RV32IFD-LABEL: <f_medium_ledge_pos>:
; RV32IFD: addi [[REG:.*]], zero, 0x20
; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
; RV32IFD: addi [[REG:.*]], zero, 0x21
; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @f_medium_ledge_pos(i32 %in0) minsize {
%cmp = icmp CMPCOND i32 %in0, 32
%cmp = icmp CMPCOND i32 %in0, 33
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@preames preames Sep 17, 2024

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The test delta in this file needs a bit of explanation. Most of the diff is me trying to understand the testing to find the actual problem. The only actual change is this line.

Essentially, the original test is confused about what's it's testing. "32" can be handled via the c.addi offset scheme. However, here's the originally assembly we got:

	addi	a1, a0, -32
	li	a0, -99
	bnez	a1, .LBB0_2
# %bb.1:
	li	a0, 42
.LBB0_2:
	ret

Note that the c.addi form can only be matched when source and destination register are the same.

One this change sinks the unrelated LI out of the way, the register allocator can do that, and we end up with a compressed addi.

From the naming of the test and the comment, this doesn't appear to have been the intended result, and thus I adjusted the constant to 33. If reviewers agree that this is the right test update, I'm going to land a rework of this test file separately.

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@topperc topperc Sep 17, 2024

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I agree this is the right test update.

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@preames preames Sep 17, 2024

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I landed these changes on main, and eventually figured out we could autogen this test without loosing the spirit of the compressed checks. The resulting diff (there is a much bigger one than even I'd realized) should be a lot more obvious now. They do look to be improvements.

%toRet = select i1 %cmp, i32 -99, i32 42
ret i32 %toRet
}
Expand All @@ -107,11 +103,11 @@ define i32 @f_medium_ledge_pos(i32 %in0) minsize {
; but fit in 12 bit (imm)
; RV32IFDC-LABEL: <f_medium_ledge_neg>:
; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], 0x21
; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]]
; RV32IFDC: [[COND:c.b.*]] [[MAYZEROREG]], [[PLACE:.*]]
; --- no compress extension
; RV32IFD-LABEL: <f_medium_ledge_neg>:
; RV32IFD: addi [[REG:.*]], zero, -0x21
; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @f_medium_ledge_neg(i32 %in0) minsize {
%cmp = icmp CMPCOND i32 %in0, -33
%toRet = select i1 %cmp, i32 -99, i32 42
Expand All @@ -122,11 +118,11 @@ define i32 @f_medium_ledge_neg(i32 %in0) minsize {
; but fit in 12 bit (imm)
; RV32IFDC-LABEL: <f_medium_pos>:
; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], -0x3f
; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]]
; RV32IFDC: [[COND:c.b.*]] [[MAYZEROREG]], [[PLACE:.*]]
; --- no compress extension
; RV32IFD-LABEL: <f_medium_pos>:
; RV32IFD: addi [[REG:.*]], zero, 0x3f
; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @f_medium_pos(i32 %in0) minsize {
%cmp = icmp CMPCOND i32 %in0, 63
%toRet = select i1 %cmp, i32 -99, i32 42
Expand All @@ -137,11 +133,11 @@ define i32 @f_medium_pos(i32 %in0) minsize {
; but fit in 12 bit (imm)
; RV32IFDC-LABEL: <f_medium_neg>:
; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], 0x3f
; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]]
; RV32IFDC: [[COND:c.b.*]] [[MAYZEROREG]], [[PLACE:.*]]
; --- no compress extension
; RV32IFD-LABEL: <f_medium_neg>:
; RV32IFD: addi [[REG:.*]], zero, -0x3f
; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @f_medium_neg(i32 %in0) minsize {
%cmp = icmp CMPCOND i32 %in0, -63
%toRet = select i1 %cmp, i32 -99, i32 42
Expand All @@ -152,11 +148,11 @@ define i32 @f_medium_neg(i32 %in0) minsize {
; but fit in 12 bit (imm)
; RV32IFDC-LABEL: <f_medium_bedge_pos>:
; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], -0x7ff
; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]]
; RV32IFDC: [[COND:c.b.*]] [[MAYZEROREG]], [[PLACE:.*]]
; --- no compress extension
; RV32IFD-LABEL: <f_medium_bedge_pos>:
; RV32IFD: addi [[REG:.*]], zero, 0x7ff
; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @f_medium_bedge_pos(i32 %in0) minsize {
%cmp = icmp CMPCOND i32 %in0, 2047
%toRet = select i1 %cmp, i32 -99, i32 42
Expand All @@ -167,11 +163,11 @@ define i32 @f_medium_bedge_pos(i32 %in0) minsize {
; but fit in 12 bit (imm), negative value fit in 12 bit too.
; RV32IFDC-LABEL: <f_medium_bedge_neg>:
; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], 0x7ff
; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]]
; RV32IFDC: [[COND:c.b.*]] [[MAYZEROREG]], [[PLACE:.*]]
; --- no compress extension
; RV32IFD-LABEL: <f_medium_bedge_neg>:
; RV32IFD: addi [[REG:.*]], zero, -0x7ff
; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
; RV32IFD: [[COND:b.*]] [[ANOTHER:.*]], [[REG]], [[PLACE:.*]]
define i32 @f_medium_bedge_neg(i32 %in0) minsize {
%cmp = icmp CMPCOND i32 %in0, -2047
%toRet = select i1 %cmp, i32 -99, i32 42
Expand All @@ -180,7 +176,7 @@ define i32 @f_medium_bedge_neg(i32 %in0) minsize {

; constant is big and do not fit in 12 bit (imm), fit in i32
; RV32IFDC-LABEL: <f_big_ledge_pos>:
; RV32IFDC-NOT: RESBROPT
; RV32IFDC-NOT: c.b
; --- no compress extension
; nothing to check.
define i32 @f_big_ledge_pos(i32 %in0) minsize {
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/RISCV/machine-sink-load-immediate.ll
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Expand Up @@ -184,13 +184,13 @@ declare i32 @toupper()
define signext i32 @overlap_live_ranges(ptr %arg, i32 signext %arg1) {
; CHECK-LABEL: overlap_live_ranges:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: li a3, 1
; CHECK-NEXT: li a2, 13
; CHECK-NEXT: bne a1, a3, .LBB1_2
; CHECK-NEXT: li a2, 1
; CHECK-NEXT: bne a1, a2, .LBB1_2
; CHECK-NEXT: # %bb.1: # %bb2
; CHECK-NEXT: lw a2, 4(a0)
; CHECK-NEXT: .LBB1_2: # %bb5
; CHECK-NEXT: mv a0, a2
; CHECK-NEXT: lw a0, 4(a0)
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: li a0, 13
; CHECK-NEXT: ret
bb:
%i = icmp eq i32 %arg1, 1
Expand Down
10 changes: 4 additions & 6 deletions llvm/test/CodeGen/RISCV/rv64m-w-insts-legalization.ll
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Expand Up @@ -5,15 +5,13 @@ define signext i32 @mulw(i32 signext %s, i32 signext %n, i32 signext %k) nounwin
; CHECK-LABEL: mulw:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li a2, 1
; CHECK-NEXT: bge a0, a1, .LBB0_3
; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: li a2, 1
; CHECK-NEXT: .LBB0_2: # %for.body
; CHECK-NEXT: bge a0, a1, .LBB0_2
; CHECK-NEXT: .LBB0_1: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: mulw a2, a0, a2
; CHECK-NEXT: addiw a0, a0, 1
; CHECK-NEXT: blt a0, a1, .LBB0_2
; CHECK-NEXT: .LBB0_3: # %for.cond.cleanup
; CHECK-NEXT: blt a0, a1, .LBB0_1
; CHECK-NEXT: .LBB0_2: # %for.cond.cleanup
; CHECK-NEXT: mv a0, a2
; CHECK-NEXT: ret
entry:
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/RISCV/select-const.ll
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Expand Up @@ -61,22 +61,22 @@ define signext i32 @select_const_int_pow2_zero(i1 zeroext %a) nounwind {
define signext i32 @select_const_int_harder(i1 zeroext %a) nounwind {
; RV32-LABEL: select_const_int_harder:
; RV32: # %bb.0:
; RV32-NEXT: mv a1, a0
; RV32-NEXT: li a0, 6
; RV32-NEXT: bnez a1, .LBB3_2
; RV32-NEXT: bnez a0, .LBB3_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a0, 38
; RV32-NEXT: ret
; RV32-NEXT: .LBB3_2:
; RV32-NEXT: li a0, 6
; RV32-NEXT: ret
;
; RV64-LABEL: select_const_int_harder:
; RV64: # %bb.0:
; RV64-NEXT: mv a1, a0
; RV64-NEXT: li a0, 6
; RV64-NEXT: bnez a1, .LBB3_2
; RV64-NEXT: bnez a0, .LBB3_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a0, 38
; RV64-NEXT: ret
; RV64-NEXT: .LBB3_2:
; RV64-NEXT: li a0, 6
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@preames preames Sep 16, 2024

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These select lowering changes are arguably real regressions. We are loosing the opportunity to allocate the untaken result into a register and then conditionally overwrite it. The tail duplication probably wouldn't happen in real code, so we'd end up emitting an extra unconditional jump to bypass the critical edge we split before the join.

Specifically for these selects in tests, most can be done via arithmetic expansions instead. I started to implement that, but ended up pulling on a few too many intertwined changes. I do plan to go back to this, but I don't consider the select impact blocking here.

; RV64-NEXT: ret
%1 = select i1 %a, i32 6, i32 38
ret i32 %1
Expand Down
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