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[RISCV][GISEL] regbankselect for G_VMCLR_VL #110746

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Merged
merged 1 commit into from
Oct 2, 2024
Merged

[RISCV][GISEL] regbankselect for G_VMCLR_VL #110746

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149 changes: 149 additions & 0 deletions llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/vmclr.mir
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Original file line number Diff line number Diff line change
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV32I %s
# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \
# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
# RUN: -o - | FileCheck -check-prefix=RV64I %s

---
name: splat_zero_nxv1i1
legalized: true
regBankSelected: false
body: |
bb.1:
; RV32I-LABEL: name: splat_zero_nxv1i1
; RV32I: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 1 x s1>) = G_VMCLR_VL $x0
; RV32I-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 1 x s1>)
; RV32I-NEXT: PseudoRET implicit $v0
;
; RV64I-LABEL: name: splat_zero_nxv1i1
; RV64I: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 1 x s1>) = G_VMCLR_VL $x0
; RV64I-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 1 x s1>)
; RV64I-NEXT: PseudoRET implicit $v0
%0:_(<vscale x 1 x s1>) = G_VMCLR_VL $x0
$v0 = COPY %0(<vscale x 1 x s1>)
PseudoRET implicit $v0

...
---
name: splat_zero_nxv2i1
legalized: true
regBankSelected: false
body: |
bb.1:
; RV32I-LABEL: name: splat_zero_nxv2i1
; RV32I: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 2 x s1>) = G_VMCLR_VL $x0
; RV32I-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 2 x s1>)
; RV32I-NEXT: PseudoRET implicit $v0
;
; RV64I-LABEL: name: splat_zero_nxv2i1
; RV64I: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 2 x s1>) = G_VMCLR_VL $x0
; RV64I-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 2 x s1>)
; RV64I-NEXT: PseudoRET implicit $v0
%0:_(<vscale x 2 x s1>) = G_VMCLR_VL $x0
$v0 = COPY %0(<vscale x 2 x s1>)
PseudoRET implicit $v0

...
---
name: splat_zero_nxv4i1
legalized: true
regBankSelected: false
body: |
bb.1:
; RV32I-LABEL: name: splat_zero_nxv4i1
; RV32I: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 4 x s1>) = G_VMCLR_VL $x0
; RV32I-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 4 x s1>)
; RV32I-NEXT: PseudoRET implicit $v0
;
; RV64I-LABEL: name: splat_zero_nxv4i1
; RV64I: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 4 x s1>) = G_VMCLR_VL $x0
; RV64I-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 4 x s1>)
; RV64I-NEXT: PseudoRET implicit $v0
%0:_(<vscale x 4 x s1>) = G_VMCLR_VL $x0
$v0 = COPY %0(<vscale x 4 x s1>)
PseudoRET implicit $v0

...
---
name: splat_zero_nxv8i1
legalized: true
regBankSelected: false
body: |
bb.1:
; RV32I-LABEL: name: splat_zero_nxv8i1
; RV32I: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 8 x s1>) = G_VMCLR_VL $x0
; RV32I-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 8 x s1>)
; RV32I-NEXT: PseudoRET implicit $v0
;
; RV64I-LABEL: name: splat_zero_nxv8i1
; RV64I: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 8 x s1>) = G_VMCLR_VL $x0
; RV64I-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 8 x s1>)
; RV64I-NEXT: PseudoRET implicit $v0
%0:_(<vscale x 8 x s1>) = G_VMCLR_VL $x0
$v0 = COPY %0(<vscale x 8 x s1>)
PseudoRET implicit $v0

...
---
name: splat_zero_nxv16i1
legalized: true
regBankSelected: false
body: |
bb.1:
; RV32I-LABEL: name: splat_zero_nxv16i1
; RV32I: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 16 x s1>) = G_VMCLR_VL $x0
; RV32I-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 16 x s1>)
; RV32I-NEXT: PseudoRET implicit $v0
;
; RV64I-LABEL: name: splat_zero_nxv16i1
; RV64I: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 16 x s1>) = G_VMCLR_VL $x0
; RV64I-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 16 x s1>)
; RV64I-NEXT: PseudoRET implicit $v0
%0:_(<vscale x 16 x s1>) = G_VMCLR_VL $x0
$v0 = COPY %0(<vscale x 16 x s1>)
PseudoRET implicit $v0

...
---
name: splat_zero_nxv32i1
legalized: true
regBankSelected: false
body: |
bb.1:
; RV32I-LABEL: name: splat_zero_nxv32i1
; RV32I: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 32 x s1>) = G_VMCLR_VL $x0
; RV32I-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 32 x s1>)
; RV32I-NEXT: PseudoRET implicit $v0
;
; RV64I-LABEL: name: splat_zero_nxv32i1
; RV64I: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 32 x s1>) = G_VMCLR_VL $x0
; RV64I-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 32 x s1>)
; RV64I-NEXT: PseudoRET implicit $v0
%0:_(<vscale x 32 x s1>) = G_VMCLR_VL $x0
$v0 = COPY %0(<vscale x 32 x s1>)
PseudoRET implicit $v0

...
---
name: splat_zero_nxv64i1
legalized: true
regBankSelected: false
body: |
bb.1:
; RV32I-LABEL: name: splat_zero_nxv64i1
; RV32I: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 64 x s1>) = G_VMCLR_VL $x0
; RV32I-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 64 x s1>)
; RV32I-NEXT: PseudoRET implicit $v0
;
; RV64I-LABEL: name: splat_zero_nxv64i1
; RV64I: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 64 x s1>) = G_VMCLR_VL $x0
; RV64I-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 64 x s1>)
; RV64I-NEXT: PseudoRET implicit $v0
%0:_(<vscale x 64 x s1>) = G_VMCLR_VL $x0
$v0 = COPY %0(<vscale x 64 x s1>)
PseudoRET implicit $v0

...

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