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[RISCV] Remove support for pre-RA vsetvli insertion #110796

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Merged
merged 1 commit into from
Oct 28, 2024
Merged

[RISCV] Remove support for pre-RA vsetvli insertion #110796

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11 changes: 2 additions & 9 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -179,17 +179,10 @@ bool RISCVInstrInfo::isReallyTriviallyReMaterializable(
case RISCV::VMV_S_X:
case RISCV::VFMV_S_F:
case RISCV::VID_V:
if (MI.getOperand(1).isUndef() &&
/* After RISCVInsertVSETVLI most pseudos will have implicit uses on vl
and vtype. Make sure we only rematerialize before RISCVInsertVSETVLI
i.e. -riscv-vsetvl-after-rvv-regalloc=true */
!MI.hasRegisterImplicitUseOperand(RISCV::VTYPE))
return true;
break;
return MI.getOperand(1).isUndef();
default:
break;
return TargetInstrInfo::isReallyTriviallyReMaterializable(MI);
}
return TargetInstrInfo::isReallyTriviallyReMaterializable(MI);
}

static bool forwardCopyWillClobberTuple(unsigned DstReg, unsigned SrcReg,
Expand Down
20 changes: 2 additions & 18 deletions llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -99,11 +99,6 @@ static cl::opt<bool> EnableMISchedLoadStoreClustering(
cl::desc("Enable load and store clustering in the machine scheduler"),
cl::init(true));

static cl::opt<bool> EnableVSETVLIAfterRVVRegAlloc(
"riscv-vsetvl-after-rvv-regalloc", cl::Hidden,
cl::desc("Insert vsetvls after vector register allocation"),
cl::init(true));

static cl::opt<bool>
EnableVLOptimizer("riscv-enable-vl-optimizer",
cl::desc("Enable the RISC-V VL Optimizer pass"),
Expand Down Expand Up @@ -413,8 +408,7 @@ FunctionPass *RISCVPassConfig::createRVVRegAllocPass(bool Optimized) {

bool RISCVPassConfig::addRegAssignAndRewriteFast() {
addPass(createRVVRegAllocPass(false));
if (EnableVSETVLIAfterRVVRegAlloc)
addPass(createRISCVInsertVSETVLIPass());
addPass(createRISCVInsertVSETVLIPass());
if (TM->getOptLevel() != CodeGenOptLevel::None &&
EnableRISCVDeadRegisterElimination)
addPass(createRISCVDeadRegisterDefinitionsPass());
Expand All @@ -424,8 +418,7 @@ bool RISCVPassConfig::addRegAssignAndRewriteFast() {
bool RISCVPassConfig::addRegAssignAndRewriteOptimized() {
addPass(createRVVRegAllocPass(true));
addPass(createVirtRegRewriter(false));
if (EnableVSETVLIAfterRVVRegAlloc)
addPass(createRISCVInsertVSETVLIPass());
addPass(createRISCVInsertVSETVLIPass());
if (TM->getOptLevel() != CodeGenOptLevel::None &&
EnableRISCVDeadRegisterElimination)
addPass(createRISCVDeadRegisterDefinitionsPass());
Expand Down Expand Up @@ -575,15 +568,6 @@ void RISCVPassConfig::addPreRegAlloc() {
addPass(createRISCVInsertReadWriteCSRPass());
addPass(createRISCVInsertWriteVXRMPass());
addPass(createRISCVLandingPadSetupPass());

// Run RISCVInsertVSETVLI after PHI elimination. On O1 and above do it after
// register coalescing so needVSETVLIPHI doesn't need to look through COPYs.
if (!EnableVSETVLIAfterRVVRegAlloc) {
if (TM->getOptLevel() == CodeGenOptLevel::None)
insertPass(&PHIEliminationID, &RISCVInsertVSETVLIID);
else
insertPass(&RegisterCoalescerID, &RISCVInsertVSETVLIID);
}
}

void RISCVPassConfig::addFastRegAlloc() {
Expand Down
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