[AMDGPU][True16][CodeGen] fp conversion instructions in true/fake16 f…

[broxigarchen]

…ormat

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⚠️ C/C++ code formatter, clang-format found issues in your code. ⚠️

You can test this locally with the following command:

git-clang-format --diff ae5bd2a9f292037c605b2ec0ee31200581bd8701 f0ec9e117d1b245fae0664fcc42439ebda93f4df --extensions cpp -- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

View the diff from clang-format here.

diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 982f22cf55..8c59f78374 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -7362,23 +7362,23 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist,
     Register TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
     Register NewDst = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
     if (ST.useRealTrue16Insts()) {
-        BuildMI(*MBB, Inst, DL, get(AMDGPU::COPY), TmpReg)
-            .add(Inst.getOperand(1));
-        BuildMI(*MBB, Inst, DL, get(NewOpcode), NewDst)
-            .addImm(0) // src0_modifiers
-            .addReg(TmpReg, 0, AMDGPU::hi16)
-            .addImm(0) // clamp
-            .addImm(0) // omod
-            .addImm(0); // op_sel0
+      BuildMI(*MBB, Inst, DL, get(AMDGPU::COPY), TmpReg)
+          .add(Inst.getOperand(1));
+      BuildMI(*MBB, Inst, DL, get(NewOpcode), NewDst)
+          .addImm(0) // src0_modifiers
+          .addReg(TmpReg, 0, AMDGPU::hi16)
+          .addImm(0)  // clamp
+          .addImm(0)  // omod
+          .addImm(0); // op_sel0
     } else {
-        BuildMI(*MBB, Inst, DL, get(AMDGPU::V_LSHRREV_B32_e64), TmpReg)
-            .addImm(16)
-            .add(Inst.getOperand(1));
-        BuildMI(*MBB, Inst, DL, get(NewOpcode), NewDst)
-            .addImm(0) // src0_modifiers
-            .addReg(TmpReg)
-            .addImm(0)  // clamp
-            .addImm(0); // omod
+      BuildMI(*MBB, Inst, DL, get(AMDGPU::V_LSHRREV_B32_e64), TmpReg)
+          .addImm(16)
+          .add(Inst.getOperand(1));
+      BuildMI(*MBB, Inst, DL, get(NewOpcode), NewDst)
+          .addImm(0) // src0_modifiers
+          .addReg(TmpReg)
+          .addImm(0)  // clamp
+          .addImm(0); // omod
     }
 
     MRI.replaceRegWith(Inst.getOperand(0).getReg(), NewDst);