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AMDGPU: Try to reuse dest reg for s_add_i32 frame indexes #111201

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Merged
merged 1 commit into from
Oct 7, 2024
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AMDGPU: Try to reuse dest reg for s_add_i32 frame indexes #111201

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13 changes: 10 additions & 3 deletions llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2678,12 +2678,18 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,

Register TmpReg;

// FIXME: Scavenger should figure out that the result register is
// available. Also should do this for the v_add case.
if (OtherOp.isReg() && OtherOp.getReg() != DstOp.getReg())
TmpReg = DstOp.getReg();

if (FrameReg && !ST.enableFlatScratch()) {
// FIXME: In the common case where the add does not also read its result
// (i.e. this isn't a reg += fi), it's not finding the dest reg as
// available.
TmpReg = RS->scavengeRegisterBackwards(AMDGPU::SReg_32_XM0RegClass, MI,
false, 0);
if (!TmpReg)
TmpReg = RS->scavengeRegisterBackwards(AMDGPU::SReg_32_XM0RegClass,
MI, false, 0);
BuildMI(*MBB, *MI, DL, TII->get(AMDGPU::S_LSHR_B32))
.addDef(TmpReg, RegState::Renamable)
.addReg(FrameReg)
Expand Down Expand Up @@ -2711,7 +2717,8 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,

if (!TmpReg && MaterializedReg == FrameReg) {
TmpReg = RS->scavengeRegisterBackwards(AMDGPU::SReg_32_XM0RegClass,
MI, false, 0);
MI, /*RestoreAfter=*/false, 0,
/*AllowSpill=*/false);
DstReg = TmpReg;
}

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