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Merged
merged 8 commits into from
Jul 20, 2025
Merged

[lld] Add thunks for hexagon #111217

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cced3c5
[lld] Add thunks for hexagon
androm3da Jun 25, 2025
e3b915a
needsThunk()
androm3da Jun 25, 2025
9b8059e
Add thunk range test cases
androm3da Jun 25, 2025
ea13019
fixes from review
androm3da Jul 15, 2025
58d735c
Re-format test to limit changes required
androm3da Jul 15, 2025
8a97197
remove FIXME, delete comment
androm3da Jul 19, 2025
061758b
Use --no-show-raw-insn and move the addrs to after the label
androm3da Jul 20, 2025
b7e019b
Fix jump/call targets
androm3da Jul 20, 2025
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47 changes: 47 additions & 0 deletions lld/ELF/Arch/Hexagon.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@
#include "Symbols.h"
#include "SyntheticSections.h"
#include "Target.h"
#include "Thunks.h"
#include "lld/Common/ErrorHandler.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/BinaryFormat/ELF.h"
Expand All @@ -36,6 +37,10 @@ class Hexagon final : public TargetInfo {
const uint8_t *loc) const override;
RelType getDynRel(RelType type) const override;
int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override;
bool needsThunk(RelExpr expr, RelType type, const InputFile *file,
uint64_t branchAddr, const Symbol &s,
int64_t a) const override;
bool inBranchRange(RelType type, uint64_t src, uint64_t dst) const override;
void relocate(uint8_t *loc, const Relocation &rel,
uint64_t val) const override;
void writePltHeader(uint8_t *buf) const override;
Expand Down Expand Up @@ -63,6 +68,8 @@ Hexagon::Hexagon(Ctx &ctx) : TargetInfo(ctx) {
tlsGotRel = R_HEX_TPREL_32;
tlsModuleIndexRel = R_HEX_DTPMOD_32;
tlsOffsetRel = R_HEX_DTPREL_32;

needsThunks = true;
}

uint32_t Hexagon::calcEFlags() const {
Expand Down Expand Up @@ -258,6 +265,46 @@ static uint32_t findMaskR16(Ctx &ctx, uint32_t insn) {

static void or32le(uint8_t *p, int32_t v) { write32le(p, read32le(p) | v); }

bool Hexagon::inBranchRange(RelType type, uint64_t src, uint64_t dst) const {
int64_t offset = dst - src;
switch (type) {
case llvm::ELF::R_HEX_B22_PCREL:
case llvm::ELF::R_HEX_PLT_B22_PCREL:
case llvm::ELF::R_HEX_GD_PLT_B22_PCREL:
case llvm::ELF::R_HEX_LD_PLT_B22_PCREL:
return llvm::isInt<22>(offset >> 2);
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We need tests to test the thunk range. aarch64-thunk-pi.s ppc64-long-branch.s are examples to test the exact range.

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I will add the necessary tests.

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range test cases added

case llvm::ELF::R_HEX_B15_PCREL:
return llvm::isInt<15>(offset >> 2);
break;
case llvm::ELF::R_HEX_B13_PCREL:
return llvm::isInt<13>(offset >> 2);
break;
case llvm::ELF::R_HEX_B9_PCREL:
return llvm::isInt<9>(offset >> 2);
default:
return true;
}
llvm_unreachable("unsupported relocation");
}

bool Hexagon::needsThunk(RelExpr expr, RelType type, const InputFile *file,
uint64_t branchAddr, const Symbol &s,
int64_t a) const {
// Only check branch range for supported branch relocation types
switch (type) {
case R_HEX_B22_PCREL:
case R_HEX_PLT_B22_PCREL:
case R_HEX_GD_PLT_B22_PCREL:
case R_HEX_LD_PLT_B22_PCREL:
case R_HEX_B15_PCREL:
case R_HEX_B13_PCREL:
case R_HEX_B9_PCREL:
return !ctx.target->inBranchRange(type, branchAddr, s.getVA(ctx, a));
default:
return false;
}
}

void Hexagon::relocate(uint8_t *loc, const Relocation &rel,
uint64_t val) const {
switch (rel.type) {
Expand Down
53 changes: 40 additions & 13 deletions lld/ELF/Relocations.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2140,17 +2140,44 @@ void ThunkCreator::mergeThunks(ArrayRef<OutputSection *> outputSections) {
});
}

static int64_t getPCBias(Ctx &ctx, RelType type) {
if (ctx.arg.emachine != EM_ARM)
return 0;
switch (type) {
case R_ARM_THM_JUMP19:
case R_ARM_THM_JUMP24:
case R_ARM_THM_CALL:
return 4;
default:
return 8;
constexpr uint32_t HEXAGON_MASK_END_PACKET = 3 << 14;
constexpr uint32_t HEXAGON_END_OF_PACKET = 3 << 14;
constexpr uint32_t HEXAGON_END_OF_DUPLEX = 0 << 14;

// Return the distance between the packet start and the instruction in the
// relocation.
static int getHexagonPacketOffset(const InputSection &isec,
const Relocation &rel) {
const ArrayRef<uint8_t> data = isec.content();

// Search back as many as 3 instructions.
for (unsigned i = 0;; i++) {
if (i == 3 || rel.offset < (i + 1) * 4)
return i * 4;
uint32_t instWord = 0;
const ArrayRef<uint8_t> instWordContents =
data.drop_front(rel.offset - (i + 1) * 4);
memcpy(&instWord, instWordContents.data(), sizeof(instWord));
if (((instWord & HEXAGON_MASK_END_PACKET) == HEXAGON_END_OF_PACKET) ||
((instWord & HEXAGON_MASK_END_PACKET) == HEXAGON_END_OF_DUPLEX))
return i * 4;
}
}
static int64_t getPCBias(Ctx &ctx, const InputSection &isec,
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blank line between functions

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fixed

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This was not fixed

const Relocation &rel) {
if (ctx.arg.emachine == EM_ARM) {
switch (rel.type) {
case R_ARM_THM_JUMP19:
case R_ARM_THM_JUMP24:
case R_ARM_THM_CALL:
return 4;
default:
return 8;
}
}
if (ctx.arg.emachine == EM_HEXAGON)
return -getHexagonPacketOffset(isec, rel);
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https://llvm.org/docs/CodingStandards.html#don-t-use-braces-on-simple-single-statement-bodies-of-if-else-loop-statements

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fixed, thank you.

return 0;
}

// Find or create a ThunkSection within the InputSectionDescription (ISD) that
Expand All @@ -2162,7 +2189,7 @@ ThunkSection *ThunkCreator::getISDThunkSec(OutputSection *os,
const Relocation &rel,
uint64_t src) {
// See the comment in getThunk for -pcBias below.
const int64_t pcBias = getPCBias(ctx, rel.type);
const int64_t pcBias = getPCBias(ctx, *isec, rel);
for (std::pair<ThunkSection *, uint32_t> tp : isd->thunkSections) {
ThunkSection *ts = tp.first;
uint64_t tsBase = os->addr + ts->outSecOff - pcBias;
Expand Down Expand Up @@ -2323,7 +2350,7 @@ std::pair<Thunk *, bool> ThunkCreator::getThunk(InputSection *isec,
// out in the relocation addend. We compensate for the PC bias so that
// an Arm and Thumb relocation to the same destination get the same keyAddend,
// which is usually 0.
const int64_t pcBias = getPCBias(ctx, rel.type);
const int64_t pcBias = getPCBias(ctx, *isec, rel);
const int64_t keyAddend = rel.addend + pcBias;

// We use a ((section, offset), addend) pair to find the thunk position if
Expand Down Expand Up @@ -2482,7 +2509,7 @@ bool ThunkCreator::createThunks(uint32_t pass,
// STT_SECTION + non-zero addend, clear the addend after
// redirection.
if (ctx.arg.emachine != EM_MIPS)
rel.addend = -getPCBias(ctx, rel.type);
rel.addend = -getPCBias(ctx, *isec, rel);
}

for (auto &p : isd->thunkSections)
Expand Down
72 changes: 71 additions & 1 deletion lld/ELF/Thunks.cpp
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Expand Up @@ -415,6 +415,22 @@ class AVRThunk : public Thunk {
void addSymbols(ThunkSection &isec) override;
};

// Hexagon CPUs need thunks for R_HEX_B{9,1{3,5},22}_PCREL,
// R_HEX_{,GD_}PLT_B22_PCREL when their destination is out of
// range.
class HexagonThunk : public Thunk {
public:
HexagonThunk(Ctx &ctx, const InputSection &isec, Relocation &rel,
Symbol &dest)
: Thunk(ctx, dest, 0), relOffset(rel.offset) {
alignment = 4;
}
uint32_t relOffset;
uint32_t size() override { return ctx.arg.isPic ? 12 : 8; }
void writeTo(uint8_t *buf) override;
void addSymbols(ThunkSection &isec) override;
};

// MIPS LA25 thunk
class MipsThunk final : public Thunk {
public:
Expand Down Expand Up @@ -1519,6 +1535,39 @@ bool PPC64LongBranchThunk::isCompatibleWith(const InputSection &isec,
return rel.type == R_PPC64_REL24 || rel.type == R_PPC64_REL14;
}

// Hexagon Target Thunks
static uint64_t getHexagonThunkDestVA(Ctx &ctx, const Symbol &s, int64_t a) {
uint64_t v = s.isInPlt(ctx) ? s.getPltVA(ctx) : s.getVA(ctx, a);
return SignExtend64<32>(v);
}

void HexagonThunk::writeTo(uint8_t *buf) {
uint64_t s = getHexagonThunkDestVA(ctx, destination, addend);
uint64_t p = getThunkTargetSym()->getVA(ctx);

if (ctx.arg.isPic) {
write32(ctx, buf + 0, 0x00004000); // { immext(#0)
ctx.target->relocateNoSym(buf, R_HEX_B32_PCREL_X, s - p);
write32(ctx, buf + 4, 0x6a49c00e); // r14 = add(pc,##0) }
ctx.target->relocateNoSym(buf + 4, R_HEX_6_PCREL_X, s - p);

write32(ctx, buf + 8, 0x528ec000); // { jumpr r14 }
} else {
write32(ctx, buf + 0, 0x00004000); // { immext
ctx.target->relocateNoSym(buf, R_HEX_B32_PCREL_X, s - p);
write32(ctx, buf + 4, 0x5800c000); // jump <> }
ctx.target->relocateNoSym(buf + 4, R_HEX_B22_PCREL_X, s - p);
}
}
void HexagonThunk::addSymbols(ThunkSection &isec) {
Symbol *enclosing = isec.getEnclosingSymbol(relOffset);
StringRef src = enclosing ? enclosing->getName() : isec.name;

addSymbol(
saver().save("__hexagon_thunk_" + destination.getName() + "_from_" + src),
STT_FUNC, 0, isec);
}

Thunk::Thunk(Ctx &ctx, Symbol &d, int64_t a)
: ctx(ctx), destination(d), addend(a), offset(0) {
destination.thunkAccessed = true;
Expand Down Expand Up @@ -1692,6 +1741,24 @@ static std::unique_ptr<Thunk> addThunkAVR(Ctx &ctx, RelType type, Symbol &s,
}
}

static std::unique_ptr<Thunk> addThunkHexagon(Ctx &ctx,
const InputSection &isec,
Relocation &rel, Symbol &s) {
switch (rel.type) {
case R_HEX_B9_PCREL:
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In needsThunk you list 7 relocation types

case R_HEX_B22_PCREL:
case R_HEX_PLT_B22_PCREL:
case R_HEX_GD_PLT_B22_PCREL:
case R_HEX_LD_PLT_B22_PCREL:
case R_HEX_B15_PCREL:
case R_HEX_B13_PCREL:
case R_HEX_B9_PCREL:

Here are only 6. Please fix it and don't add Fatal. It should just be unreachable. ARM has Fatal because it has complex microarch thunk logic, so some erroneous code paths are technically reachable.

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fixed

case R_HEX_B13_PCREL:
case R_HEX_B15_PCREL:
case R_HEX_B22_PCREL:
case R_HEX_PLT_B22_PCREL:
case R_HEX_GD_PLT_B22_PCREL:
return std::make_unique<HexagonThunk>(ctx, isec, rel, s);
default:
Fatal(ctx) << "unrecognized relocation " << rel.type << " to " << &s
<< " for hexagon target";
llvm_unreachable("");
}
}

static std::unique_ptr<Thunk> addThunkMips(Ctx &ctx, RelType type, Symbol &s) {
if ((s.stOther & STO_MIPS_MICROMIPS) && isMipsR6(ctx))
return std::make_unique<MicroMipsR6Thunk>(ctx, s);
Expand Down Expand Up @@ -1761,8 +1828,11 @@ std::unique_ptr<Thunk> elf::addThunk(Ctx &ctx, const InputSection &isec,
return addThunkPPC32(ctx, isec, rel, s);
case EM_PPC64:
return addThunkPPC64(ctx, rel.type, s, a);
case EM_HEXAGON:
return addThunkHexagon(ctx, isec, rel, s);
default:
llvm_unreachable("add Thunk only supported for ARM, AVR, Mips and PowerPC");
llvm_unreachable(
"add Thunk only supported for ARM, AVR, Hexagon, Mips and PowerPC");
}
}

Expand Down
32 changes: 0 additions & 32 deletions lld/test/ELF/hexagon-jump-error.s
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