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[PowerPC] hoist xxspltiw instruction out of the loop with FMA mutation pass. #111696

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Merged
merged 1 commit into from
Jun 5, 2025
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[PowerPC] hoist xxspltiw instruction out of the loop with FMA mutation pass. #111696

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3 changes: 2 additions & 1 deletion llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -561,7 +561,8 @@ void PPCPassConfig::addMachineSSAOptimization() {

void PPCPassConfig::addPreRegAlloc() {
if (getOptLevel() != CodeGenOptLevel::None) {
insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
insertPass(VSXFMAMutateEarly ? &TwoAddressInstructionPassID
: &MachineSchedulerID,
&PPCVSXFMAMutateID);
}

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12 changes: 6 additions & 6 deletions llvm/test/CodeGen/PowerPC/vsx-fma-m-early.ll
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Expand Up @@ -69,14 +69,14 @@ declare <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float>, <4 x float>)
; CHECK64-NEXT: bltlr cr0
; CHECK64-NEXT: # %bb.1: # %for.body.preheader
; CHECK64-NEXT: xxspltiw vs0, 1069066811
; CHECK64-NEXT: xxspltiw vs1, 1170469888
; CHECK64-NEXT: mtctr r5
; CHECK64-NEXT: li r5, 0
; CHECK64-NEXT: {{.*}}align 5
; CHECK64-NEXT: [[L2_bar:.*]]: # %for.body
; CHECK64-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK64-NEXT: lxvx vs1, r4, r5
; CHECK64-NEXT: xxspltiw vs2, 1170469888
; CHECK64-NEXT: xvmaddasp vs2, vs1, vs0
; CHECK64-NEXT: lxvx vs2, r4, r5
; CHECK64-NEXT: xvmaddmsp vs2, vs0, vs1
; CHECK64-NEXT: stxvx vs2, r3, r5
; CHECK64-NEXT: addi r5, r5, 16
; CHECK64-NEXT: bdnz [[L2_bar]]
Expand Down Expand Up @@ -139,17 +139,17 @@ declare <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float>, <4 x float>)
; CHECK32-NEXT: blelr cr0
; CHECK32-NEXT: # %bb.1: # %for.body.preheader
; CHECK32-NEXT: xxspltiw vs0, 1069066811
; CHECK32-NEXT: xxspltiw vs1, 1170469888
; CHECK32-NEXT: li r6, 0
; CHECK32-NEXT: li r7, 0
; CHECK32-NEXT: .align 4
; CHECK32-NEXT: [[L2_foo:.*]]: # %for.body
; CHECK32-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK32-NEXT: slwi r8, r7, 4
; CHECK32-NEXT: xxspltiw vs2, 1170469888
; CHECK32-NEXT: addic r7, r7, 1
; CHECK32-NEXT: addze r6, r6
; CHECK32-NEXT: lxvx vs1, r4, r8
; CHECK32-NEXT: xvmaddasp vs2, vs1, vs0
; CHECK32-NEXT: lxvx vs2, r4, r8
; CHECK32-NEXT: xvmaddmsp vs2, vs0, vs1
; CHECK32-NEXT: stxvx vs2, r3, r8
; CHECK32-NEXT: xor r8, r7, r5
; CHECK32-NEXT: or. r8, r8, r6
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