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[DAGCombiner] Fix check for extending loads #112182
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[DAGCombiner] Fix check for extending loads #112182
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@llvm/pr-subscribers-backend-aarch64 @llvm/pr-subscribers-llvm-selectiondag Author: Lewis Crawford (LewisCrawford) ChangesFix a check for extending loads in DAGCombiner, All backends apart from AArch64 ignore this Full diff: https://github.com/llvm/llvm-project/pull/112182.diff 2 Files Affected:
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 810ca458bc8787..2d9025da5e2e85 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -22566,7 +22566,7 @@ SDValue DAGCombiner::scalarizeExtractedVectorLoad(SDNode *EVE, EVT InVecVT,
return SDValue();
ISD::LoadExtType ExtTy =
- ResultVT.bitsGT(VecEltVT) ? ISD::NON_EXTLOAD : ISD::EXTLOAD;
+ ResultVT.bitsGT(VecEltVT) ? ISD::EXTLOAD : ISD::NON_EXTLOAD;
if (!TLI.isOperationLegalOrCustom(ISD::LOAD, VecEltVT) ||
!TLI.shouldReduceLoadWidth(OriginalLoad, ExtTy, VecEltVT))
return SDValue();
diff --git a/llvm/test/CodeGen/AArch64/aarch64-scalarize-vec-load-ext.ll b/llvm/test/CodeGen/AArch64/aarch64-scalarize-vec-load-ext.ll
new file mode 100644
index 00000000000000..f34cad0b097f55
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/aarch64-scalarize-vec-load-ext.ll
@@ -0,0 +1,29 @@
+; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
+
+; FIXME: Currently, we avoid narrowing this v4i32 load, in the
+; hopes of being able to fold the shift, despite it requiring stack
+; storage + loads. Ideally, we should narrow here and load the i32
+; directly from the variable offset e.g:
+;
+; add x8, x0, x1, lsl #4
+; and x9, x2, #0x3
+; ldr w0, [x8, x9, lsl #2]
+;
+; The AArch64TargetLowering::shouldReduceLoadWidth heuristic should
+; probably be updated to choose load-narrowing instead of folding the
+; lsl in larger vector cases.
+;
+; CHECK-LABEL: narrow_load_v4_i32_single_ele_variable_idx:
+; CHECK: sub sp, sp, #16
+; CHECK: ldr q[[REG0:[0-9]+]], [x0, x1, lsl #4]
+; CHECK: bfi x[[REG1:[0-9]+]], x2, #2, #2
+; CHECK: str q[[REG0]], [sp]
+; CHECK: ldr w0, [x[[REG1]]]
+; CHECK: add sp, sp, #16
+define i32 @narrow_load_v4_i32_single_ele_variable_idx(ptr %ptr, i64 %off, i32 %ele) {
+entry:
+ %idx = getelementptr inbounds <4 x i32>, ptr %ptr, i64 %off
+ %x = load <4 x i32>, ptr %idx, align 8
+ %res = extractelement <4 x i32> %x, i32 %ele
+ ret i32 %res
+}
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| @@ -0,0 +1,29 @@ | |||
| ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s | |||
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Can you merge this test with whatever test was added in the original combine?
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And bonus points for using update_llc_test_checks.
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Fix a check for extending loads in DAGCombiner, where if the result type has more bits than the loaded type it should count as an extending load. All backends apart from AArch64 ignore this ExtTy argument to shouldReduceLoadWidth, so this change currently only impacts AArch64.
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/73/builds/7147 Here is the relevant piece of the build log for the reference |
Fix a check for extending loads in DAGCombiner,
where if the result type has more bits than the
loaded type it should count as an extending load.
All backends apart from AArch64 ignore this
ExtTy argument to shouldReduceLoadWidth, so this
change currently only impacts AArch64.