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[MLIR][NVVM] Add PTX predefined special registers #112343

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merged 1 commit into from
Oct 17, 2024
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[MLIR][NVVM] Add PTX predefined special registers #112343

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22 changes: 21 additions & 1 deletion mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
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Original file line number Diff line number Diff line change
Expand Up @@ -139,9 +139,22 @@ class NVVM_SpecialRangeableRegisterOp<string mnemonic, list<Trait> traits = []>
}

//===----------------------------------------------------------------------===//
// Lane index and range
// Lane, Warp, SM, Grid index and range
def NVVM_LaneIdOp : NVVM_SpecialRangeableRegisterOp<"read.ptx.sreg.laneid">;
def NVVM_WarpSizeOp : NVVM_SpecialRangeableRegisterOp<"read.ptx.sreg.warpsize">;
def NVVM_WarpIdOp : NVVM_SpecialRangeableRegisterOp<"read.ptx.sreg.warpid">;
def NVVM_WarpDimOp : NVVM_SpecialRangeableRegisterOp<"read.ptx.sreg.nwarpid">;
def NVVM_SmIdOp : NVVM_SpecialRangeableRegisterOp<"read.ptx.sreg.smid">;
def NVVM_SmDimOp : NVVM_SpecialRangeableRegisterOp<"read.ptx.sreg.nsmid">;
def NVVM_GridIdOp : NVVM_SpecialRangeableRegisterOp<"read.ptx.sreg.gridid">;

//===----------------------------------------------------------------------===//
// Lane Mask Comparison Ops
def NVVM_LaneMaskEqOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.lanemask.eq">;
def NVVM_LaneMaskLeOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.lanemask.le">;
def NVVM_LaneMaskLtOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.lanemask.lt">;
def NVVM_LaneMaskGeOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.lanemask.ge">;
def NVVM_LaneMaskGtOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.lanemask.gt">;

//===----------------------------------------------------------------------===//
// Thread index and range
Expand Down Expand Up @@ -189,6 +202,13 @@ def NVVM_ClusterDim : NVVM_SpecialRangeableRegisterOp<"read.ptx.sreg.cluster.nct
// Clock registers
def NVVM_ClockOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.clock">;
def NVVM_Clock64Op : NVVM_SpecialRegisterOp<"read.ptx.sreg.clock64">;
def NVVM_GlobalTimerOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.globaltimer">;

//===----------------------------------------------------------------------===//
// envreg registers
foreach index = !range(0, 32) in {
def NVVM_EnvReg # index # Op : NVVM_SpecialRegisterOp<"read.ptx.sreg.envreg" # index>;
}

//===----------------------------------------------------------------------===//
// NVVM approximate op definitions
Expand Down
92 changes: 88 additions & 4 deletions mlir/test/Target/LLVMIR/nvvmir.mlir
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Expand Up @@ -62,10 +62,94 @@ llvm.func @nvvm_special_regs() -> i32 {
%29 = nvvm.read.ptx.sreg.clock : i32
// CHECK: call i64 @llvm.nvvm.read.ptx.sreg.clock64
%30 = nvvm.read.ptx.sreg.clock64 : i64

// CHECK: %31 = call range(i32 0, 64) i32 @llvm.nvvm.read.ptx.sreg.tid.x()
%31 = nvvm.read.ptx.sreg.tid.x range <i32, 0, 64> : i32

// CHECK: call i64 @llvm.nvvm.read.ptx.sreg.globaltimer
%31 = nvvm.read.ptx.sreg.globaltimer : i64
// CHECK: %32 = call range(i32 0, 64) i32 @llvm.nvvm.read.ptx.sreg.tid.x()
%32 = nvvm.read.ptx.sreg.tid.x range <i32, 0, 64> : i32
// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.warpid
%33 = nvvm.read.ptx.sreg.warpid : i32
// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.nwarpid
%34 = nvvm.read.ptx.sreg.nwarpid : i32
// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.smid
%35 = nvvm.read.ptx.sreg.smid : i32
// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.nsmid
%36 = nvvm.read.ptx.sreg.nsmid : i32
// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.gridid
%37 = nvvm.read.ptx.sreg.gridid : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg0
%38 = nvvm.read.ptx.sreg.envreg0 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg1
%39 = nvvm.read.ptx.sreg.envreg1 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg2
%40 = nvvm.read.ptx.sreg.envreg2 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg3
%41 = nvvm.read.ptx.sreg.envreg3 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg4
%42 = nvvm.read.ptx.sreg.envreg4 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg5
%43 = nvvm.read.ptx.sreg.envreg5 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg6
%44 = nvvm.read.ptx.sreg.envreg6 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg7
%45 = nvvm.read.ptx.sreg.envreg7 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg8
%46 = nvvm.read.ptx.sreg.envreg8 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg9
%47 = nvvm.read.ptx.sreg.envreg9 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg10
%48 = nvvm.read.ptx.sreg.envreg10 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg11
%49 = nvvm.read.ptx.sreg.envreg11 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg12
%50 = nvvm.read.ptx.sreg.envreg12 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg13
%51 = nvvm.read.ptx.sreg.envreg13 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg14
%52 = nvvm.read.ptx.sreg.envreg14 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg15
%53 = nvvm.read.ptx.sreg.envreg15 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg16
%54 = nvvm.read.ptx.sreg.envreg16 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg17
%55 = nvvm.read.ptx.sreg.envreg17 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg18
%56 = nvvm.read.ptx.sreg.envreg18 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg19
%57 = nvvm.read.ptx.sreg.envreg19 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg20
%58 = nvvm.read.ptx.sreg.envreg20 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg21
%59 = nvvm.read.ptx.sreg.envreg21 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg22
%60 = nvvm.read.ptx.sreg.envreg22 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg23
%61 = nvvm.read.ptx.sreg.envreg23 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg24
%62 = nvvm.read.ptx.sreg.envreg24 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg25
%63 = nvvm.read.ptx.sreg.envreg25 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg26
%64 = nvvm.read.ptx.sreg.envreg26 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg27
%65 = nvvm.read.ptx.sreg.envreg27 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg28
%66 = nvvm.read.ptx.sreg.envreg28 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg29
%67 = nvvm.read.ptx.sreg.envreg29 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg30
%68 = nvvm.read.ptx.sreg.envreg30 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.envreg31
%69 = nvvm.read.ptx.sreg.envreg31 : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.lanemask.eq
%70 = nvvm.read.ptx.sreg.lanemask.eq : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.lanemask.le
%71 = nvvm.read.ptx.sreg.lanemask.le : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.lanemask.lt
%72 = nvvm.read.ptx.sreg.lanemask.lt : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.lanemask.ge
%73 = nvvm.read.ptx.sreg.lanemask.ge : i32
//CHECK: call i32 @llvm.nvvm.read.ptx.sreg.lanemask.gt
%74 = nvvm.read.ptx.sreg.lanemask.gt : i32
llvm.return %1 : i32
}

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