[Backend] Add clearSubtargetMap API for TargetMachine.

llvm/include/llvm/Target/TargetMachine.h

@@ -448,6 +448,9 @@ class LLVMTargetMachine : public TargetMachine {
 
   void initAsmInfo();
 
+  /// clear target specific SubtargetMap.
+  virtual void clearSubtargetMap(){};
+
 public:
   /// Get a TargetTransformInfo implementation for the target.
   ///

llvm/lib/Target/AArch64/AArch64TargetMachine.cpp

@@ -272,6 +272,8 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target() {
   initializeAArch64GlobalsTaggingPass(*PR);
 }
 
+void AArch64TargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 //===----------------------------------------------------------------------===//
 // AArch64 Lowering public interface.
 //===----------------------------------------------------------------------===//

llvm/lib/Target/AArch64/AArch64TargetMachine.h

@@ -26,6 +26,9 @@ class AArch64TargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<AArch64Subtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

@@ -938,6 +938,8 @@ bool AMDGPUTargetMachine::splitModule(
 // GCN Target Machine (SI+)
 //===----------------------------------------------------------------------===//
 
+void GCNTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); };
+
 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
                                    StringRef CPU, StringRef FS,
                                    const TargetOptions &Options,

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h

@@ -81,6 +81,9 @@ class GCNTargetMachine final : public AMDGPUTargetMachine {
 private:
   mutable StringMap<std::unique_ptr<GCNSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                    StringRef FS, const TargetOptions &Options,

llvm/lib/Target/AMDGPU/R600TargetMachine.cpp

@@ -50,6 +50,8 @@ static MachineSchedRegistry R600SchedRegistry("r600",
 // R600 Target Machine (R600 -> Cayman)
 //===----------------------------------------------------------------------===//
 
+void R600TargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
                                      StringRef CPU, StringRef FS,
                                      const TargetOptions &Options,

llvm/lib/Target/AMDGPU/R600TargetMachine.h

@@ -29,6 +29,9 @@ class R600TargetMachine final : public AMDGPUTargetMachine {
 private:
   mutable StringMap<std::unique_ptr<R600Subtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   R600TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                     StringRef FS, const TargetOptions &Options,

llvm/lib/Target/ARM/ARMTargetMachine.cpp

@@ -642,3 +642,5 @@ bool ARMBaseTargetMachine::parseMachineFunctionInfo(
   MF.getInfo<ARMFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
   return false;
 }
+
+void ARMBaseTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }

llvm/lib/Target/ARM/ARMTargetMachine.h

@@ -38,6 +38,9 @@ class ARMBaseTargetMachine : public LLVMTargetMachine {
   bool isLittle;
   mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,

llvm/lib/Target/CSKY/CSKYTargetMachine.cpp

@@ -96,6 +96,8 @@ MachineFunctionInfo *CSKYTargetMachine::createMachineFunctionInfo(
                                                                   STI);
 }
 
+void CSKYTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 class CSKYPassConfig : public TargetPassConfig {
 public:

llvm/lib/Target/CSKY/CSKYTargetMachine.h

@@ -24,6 +24,9 @@ class CSKYTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<CSKYSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   CSKYTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                     StringRef FS, const TargetOptions &Options,

llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp

@@ -348,6 +348,8 @@ MachineFunctionInfo *HexagonTargetMachine::createMachineFunctionInfo(
 
 HexagonTargetMachine::~HexagonTargetMachine() = default;
 
+void HexagonTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 /// Hexagon Code Generator Pass Configuration Options.
 class HexagonPassConfig : public TargetPassConfig {

llvm/lib/Target/Hexagon/HexagonTargetMachine.h

@@ -26,6 +26,9 @@ class HexagonTargetMachine : public LLVMTargetMachine {
   HexagonSubtarget Subtarget;
   mutable StringMap<std::unique_ptr<HexagonSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,

llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp

@@ -141,6 +141,8 @@ MachineFunctionInfo *LoongArchTargetMachine::createMachineFunctionInfo(
       Allocator, F, STI);
 }
 
+void LoongArchTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 class LoongArchPassConfig : public TargetPassConfig {
 public:

llvm/lib/Target/LoongArch/LoongArchTargetMachine.h

@@ -23,6 +23,9 @@ class LoongArchTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<LoongArchSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   LoongArchTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                          StringRef FS, const TargetOptions &Options,

llvm/lib/Target/M68k/M68kTargetMachine.cpp

@@ -138,6 +138,8 @@ MachineFunctionInfo *M68kTargetMachine::createMachineFunctionInfo(
                                                                   STI);
 }
 
+void M68kTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 //===----------------------------------------------------------------------===//
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//

llvm/lib/Target/M68k/M68kTargetMachine.h

@@ -34,6 +34,9 @@ class M68kTargetMachine : public LLVMTargetMachine {
 
   mutable StringMap<std::unique_ptr<M68kSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   M68kTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                     StringRef FS, const TargetOptions &Options,

llvm/lib/Target/Mips/MipsTargetMachine.cpp

@@ -215,6 +215,8 @@ void MipsTargetMachine::resetSubtarget(MachineFunction *MF) {
   Subtarget = &MF->getSubtarget<MipsSubtarget>();
 }
 
+void MipsTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 
 /// Mips Code Generator Pass Configuration Options.

llvm/lib/Target/Mips/MipsTargetMachine.h

@@ -36,6 +36,9 @@ class MipsTargetMachine : public LLVMTargetMachine {
 
   mutable StringMap<std::unique_ptr<MipsSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   MipsTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                     StringRef FS, const TargetOptions &Options,

llvm/lib/Target/PowerPC/PPCTargetMachine.cpp

@@ -410,6 +410,8 @@ PPCTargetMachine::getSubtargetImpl(const Function &F) const {
   return I.get();
 }
 
+void PPCTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 //===----------------------------------------------------------------------===//
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//

llvm/lib/Target/PowerPC/PPCTargetMachine.h

@@ -36,6 +36,9 @@ class PPCTargetMachine final : public LLVMTargetMachine {
 
   mutable StringMap<std::unique_ptr<PPCSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                    StringRef FS, const TargetOptions &Options,

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

@@ -277,6 +277,8 @@ bool RISCVTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
   return true;
 }
 
+void RISCVTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 
 class RVVRegisterRegAlloc : public RegisterRegAllocBase<RVVRegisterRegAlloc> {

llvm/lib/Target/RISCV/RISCVTargetMachine.h

@@ -25,6 +25,9 @@ class RISCVTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
   mutable StringMap<std::unique_ptr<RISCVSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                      StringRef FS, const TargetOptions &Options,

llvm/lib/Target/Sparc/SparcTargetMachine.cpp

@@ -158,6 +158,8 @@ MachineFunctionInfo *SparcTargetMachine::createMachineFunctionInfo(
                                                                     F, STI);
 }
 
+void SparcTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 /// Sparc Code Generator Pass Configuration Options.
 class SparcPassConfig : public TargetPassConfig {

llvm/lib/Target/Sparc/SparcTargetMachine.h

@@ -25,6 +25,9 @@ class SparcTargetMachine : public LLVMTargetMachine {
   bool is64Bit;
   mutable StringMap<std::unique_ptr<SparcSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   SparcTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                      StringRef FS, const TargetOptions &Options,

llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp

@@ -205,6 +205,8 @@ SystemZTargetMachine::getSubtargetImpl(const Function &F) const {
   return I.get();
 }
 
+void SystemZTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 
 /// SystemZ Code Generator Pass Configuration Options.

llvm/lib/Target/SystemZ/SystemZTargetMachine.h

@@ -29,6 +29,9 @@ class SystemZTargetMachine : public LLVMTargetMachine {
 
   mutable StringMap<std::unique_ptr<SystemZSubtarget>> SubtargetMap;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   SystemZTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                        StringRef FS, const TargetOptions &Options,

llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp

@@ -188,6 +188,8 @@ WebAssemblyTargetMachine::getSubtargetImpl(const Function &F) const {
   return getSubtargetImpl(CPU, FS);
 }
 
+void WebAssemblyTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 
 class CoalesceFeaturesAndStripAtomics final : public ModulePass {

llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h

@@ -26,6 +26,9 @@ class WebAssemblyTargetMachine final : public LLVMTargetMachine {
   mutable StringMap<std::unique_ptr<WebAssemblySubtarget>> SubtargetMap;
   bool UsesMultivalueABI = false;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   WebAssemblyTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                            StringRef FS, const TargetOptions &Options,

llvm/lib/Target/X86/X86TargetMachine.cpp

@@ -376,6 +376,8 @@ bool X86TargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
   return SrcAS < 256 && DestAS < 256;
 }
 
+void X86TargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 //===----------------------------------------------------------------------===//
 // X86 TTI query.
 //===----------------------------------------------------------------------===//

llvm/lib/Target/X86/X86TargetMachine.h

@@ -31,6 +31,9 @@ class X86TargetMachine final : public LLVMTargetMachine {
   // True if this is used in JIT.
   bool IsJIT;
 
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
+
 public:
   X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                    StringRef FS, const TargetOptions &Options,

llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp

@@ -83,6 +83,8 @@ XtensaTargetMachine::getSubtargetImpl(const Function &F) const {
   return I.get();
 }
 
+void XtensaTargetMachine::clearSubtargetMap() { SubtargetMap.clear(); }
+
 namespace {
 /// Xtensa Code Generator Pass Configuration Options.
 class XtensaPassConfig : public TargetPassConfig {

llvm/lib/Target/Xtensa/XtensaTargetMachine.h

@@ -47,6 +47,9 @@ class XtensaTargetMachine : public LLVMTargetMachine {
 
 protected:
   mutable StringMap<std::unique_ptr<XtensaSubtarget>> SubtargetMap;
+
+  /// clear target specific SubtargetMap.
+  void clearSubtargetMap() override;
 };
 } // end namespace llvm