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[NFC][X86] Fix Werror=extra error due to enum #112812

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Merged
merged 1 commit into from
Oct 18, 2024
Merged

[NFC][X86] Fix Werror=extra error due to enum #112812

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2 changes: 1 addition & 1 deletion llvm/lib/Target/X86/X86FastISel.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3544,7 +3544,7 @@ bool X86FastISel::fastLowerCall(CallLoweringInfo &CLI) {

MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(CallOpc));
if (NeedLoad)
MIB.addReg(Is64Bit ? X86::RIP : 0).addImm(1).addReg(0);
MIB.addReg(Is64Bit ? X86::RIP : X86::NoRegister).addImm(1).addReg(0);
if (Symbol)
MIB.addSym(Symbol, OpFlags);
else
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2 changes: 1 addition & 1 deletion llvm/lib/Target/X86/X86ISelLowering.cpp
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Expand Up @@ -29986,7 +29986,7 @@ static SDValue LowerShift(SDValue Op, const X86Subtarget &Subtarget,
MVT::getVectorVT(NarrowScalarVT, WideNumElts), dl, AmtWideElts);
AmtWide = DAG.getZExtOrTrunc(AmtWide, dl, WideVT);
// Perform the actual shift.
unsigned LogicalOpc = Opc == ISD::SRA ? ISD::SRL : Opc;
unsigned LogicalOpc = Opc == ISD::SRA ? (unsigned)ISD::SRL : Opc;
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@phoebewang phoebewang Oct 18, 2024

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Why need (unsigned) here? If the ISD::XXX is not a unsigned value, I think we would have more warn/error when comparing with Opc.

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@phoebewang phoebewang Oct 18, 2024

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Oh, maybe because we just use == and != here.

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@jsji jsji Oct 18, 2024

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It is about Opc is unsigned and ISD::SRL is enum, and they are used in the ?: operator, so type mismatch.

SDValue ShiftedR = DAG.getNode(LogicalOpc, dl, WideVT, RWide, AmtWide);
// Now we need to construct a mask which will "drop" bits that get
// shifted past the LSB/MSB. For a logical shift left, it will look
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