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[RISCV] Assign different scheduling classes for VMADC/VMSBC #113009

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Oct 28, 2024
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[RISCV] Assign different scheduling classes for VMADC/VMSBC #113009

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cdf809e
[RISCV] Assign different scheduling classes for VMADC/VMSBC
mshockwave Oct 19, 2024
72df45c
fixup! [RISCV] Assign different scheduling classes for VMADC/VMSBC
mshockwave Oct 21, 2024
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24 changes: 18 additions & 6 deletions llvm/lib/Target/RISCV/RISCVInstrInfoV.td
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Expand Up @@ -630,31 +630,43 @@ multiclass VMRG_IV_V_X_I<string opcodestr, bits<6> funct6> {
}

multiclass VALUm_IV_V_X<string opcodestr, bits<6> funct6> {
// if LSB of funct6 is 1, it's a mask-producing instruction that
// uses a different scheduling class.
defvar WritePrefix = !if(funct6{0}, "WriteVICALUM", "WriteVICALU");
def VM : VALUmVV<funct6, OPIVV, opcodestr # ".vvm">,
SchedBinaryMC<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV">;
SchedBinaryMC<WritePrefix#"V", "ReadVICALUV", "ReadVICALUV">;
def XM : VALUmVX<funct6, OPIVX, opcodestr # ".vxm">,
SchedBinaryMC<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX">;
SchedBinaryMC<WritePrefix#"X", "ReadVICALUV", "ReadVICALUX">;
}

multiclass VALUm_IV_V_X_I<string opcodestr, bits<6> funct6>
: VALUm_IV_V_X<opcodestr, funct6> {
// if LSB of funct6 is 1, it's a mask-producing instruction that
// uses a different scheduling class.
defvar WriteSched = !if(funct6{0}, "WriteVICALUMI", "WriteVICALUI");
def IM : VALUmVI<funct6, opcodestr # ".vim">,
SchedUnaryMC<"WriteVICALUI", "ReadVICALUV">;
SchedUnaryMC<WriteSched, "ReadVICALUV">;
}

multiclass VALUNoVm_IV_V_X<string opcodestr, bits<6> funct6> {
// if LSB of funct6 is 1, it's a mask-producing instruction that
// uses a different scheduling class.
defvar WritePrefix = !if(funct6{0}, "WriteVICALUM", "WriteVICALU");
def V : VALUVVNoVm<funct6, OPIVV, opcodestr # ".vv">,
SchedBinaryMC<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV",
SchedBinaryMC<WritePrefix#"V", "ReadVICALUV", "ReadVICALUV",
forceMasked=0>;
def X : VALUVXNoVm<funct6, OPIVX, opcodestr # ".vx">,
SchedBinaryMC<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX",
SchedBinaryMC<WritePrefix#"X", "ReadVICALUV", "ReadVICALUX",
forceMasked=0>;
}

multiclass VALUNoVm_IV_V_X_I<string opcodestr, bits<6> funct6>
: VALUNoVm_IV_V_X<opcodestr, funct6> {
// if LSB of funct6 is 1, it's a mask-producing instruction that
// uses a different scheduling class.
defvar WriteSched = !if(funct6{0}, "WriteVICALUMI", "WriteVICALUI");
def I : VALUVINoVm<funct6, opcodestr # ".vi">,
SchedUnaryMC<"WriteVICALUI", "ReadVICALUV", forceMasked=0>;
SchedUnaryMC<WriteSched, "ReadVICALUV", forceMasked=0>;
}

multiclass VALU_FV_F<string opcodestr, bits<6> funct6> {
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20 changes: 10 additions & 10 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
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Expand Up @@ -3072,13 +3072,13 @@ multiclass VPseudoVCALUM_VM_XM_IM {
defvar mx = m.MX;
defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=1, Constraint=constraint,
Commutable=1, TargetConstraintType=2>,
SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx, forceMasked=1,
SchedBinary<"WriteVICALUMV", "ReadVICALUV", "ReadVICALUV", mx, forceMasked=1,
forcePassthruRead=true>;
defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=1, Constraint=constraint, TargetConstraintType=2>,
SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx, forceMasked=1,
SchedBinary<"WriteVICALUMX", "ReadVICALUV", "ReadVICALUX", mx, forceMasked=1,
forcePassthruRead=true>;
defm "" : VPseudoBinaryV_IM<m, CarryOut=1, CarryIn=1, Constraint=constraint, TargetConstraintType=2>,
SchedUnary<"WriteVICALUI", "ReadVICALUV", mx, forceMasked=1,
SchedUnary<"WriteVICALUMI", "ReadVICALUV", mx, forceMasked=1,
forcePassthruRead=true>;
}
}
Expand All @@ -3089,11 +3089,11 @@ multiclass VPseudoVCALUM_VM_XM {
defvar mx = m.MX;
defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=1, Constraint=constraint,
TargetConstraintType=2>,
SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx, forceMasked=1,
SchedBinary<"WriteVICALUMV", "ReadVICALUV", "ReadVICALUV", mx, forceMasked=1,
forcePassthruRead=true>;
defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=1, Constraint=constraint,
TargetConstraintType=2>,
SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx, forceMasked=1,
SchedBinary<"WriteVICALUMX", "ReadVICALUV", "ReadVICALUX", mx, forceMasked=1,
forcePassthruRead=true>;
}
}
Expand All @@ -3104,13 +3104,13 @@ multiclass VPseudoVCALUM_V_X_I {
defvar mx = m.MX;
defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=0, Constraint=constraint,
Commutable=1, TargetConstraintType=2>,
SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx,
SchedBinary<"WriteVICALUMV", "ReadVICALUV", "ReadVICALUV", mx,
forcePassthruRead=true>;
defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=0, Constraint=constraint, TargetConstraintType=2>,
SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx,
SchedBinary<"WriteVICALUMX", "ReadVICALUV", "ReadVICALUX", mx,
forcePassthruRead=true>;
defm "" : VPseudoBinaryV_IM<m, CarryOut=1, CarryIn=0, Constraint=constraint>,
SchedUnary<"WriteVICALUI", "ReadVICALUV", mx,
SchedUnary<"WriteVICALUMI", "ReadVICALUV", mx,
forcePassthruRead=true>;
}
}
Expand All @@ -3120,10 +3120,10 @@ multiclass VPseudoVCALUM_V_X {
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=0, Constraint=constraint, TargetConstraintType=2>,
SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx,
SchedBinary<"WriteVICALUMV", "ReadVICALUV", "ReadVICALUV", mx,
forcePassthruRead=true>;
defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=0, Constraint=constraint, TargetConstraintType=2>,
SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx,
SchedBinary<"WriteVICALUMX", "ReadVICALUV", "ReadVICALUX", mx,
forcePassthruRead=true>;
}
}
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3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
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Expand Up @@ -631,6 +631,9 @@ foreach mx = SchedMxList in {
defm "" : LMULWriteResMX<"WriteVICALUV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICALUX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICALUI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICALUMV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICALUMX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICALUMI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVShiftV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVShiftX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVShiftI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
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Expand Up @@ -467,6 +467,9 @@ foreach mx = SchedMxList in {
defm "" : LMULWriteResMX<"WriteVICALUV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICALUX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICALUI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICALUMV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICALUMX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICALUMI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICmpV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICmpX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICmpI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
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3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
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Expand Up @@ -403,6 +403,9 @@ foreach mx = SchedMxList in {
defm "" : LMULWriteResMX<"WriteVICALUV", [SiFiveP600VectorArith], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICALUX", [SiFiveP600VectorArith], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICALUI", [SiFiveP600VectorArith], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICALUMV", [SiFiveP600VectorArith], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICALUMX", [SiFiveP600VectorArith], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICALUMI", [SiFiveP600VectorArith], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICmpV", [SiFiveP600VectorArith], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICmpX", [SiFiveP600VectorArith], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICmpI", [SiFiveP600VectorArith], mx, IsWorstCase>;
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6 changes: 6 additions & 0 deletions llvm/lib/Target/RISCV/RISCVScheduleV.td
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Expand Up @@ -364,6 +364,9 @@ defm "" : LMULSchedWrites<"WriteVExtV">;
defm "" : LMULSchedWrites<"WriteVICALUV">;
defm "" : LMULSchedWrites<"WriteVICALUX">;
defm "" : LMULSchedWrites<"WriteVICALUI">;
defm "" : LMULSchedWrites<"WriteVICALUMV">;
defm "" : LMULSchedWrites<"WriteVICALUMX">;
defm "" : LMULSchedWrites<"WriteVICALUMI">;
// 11.6. Vector Single-Width Bit Shift Instructions
defm "" : LMULSchedWrites<"WriteVShiftV">;
defm "" : LMULSchedWrites<"WriteVShiftX">;
Expand Down Expand Up @@ -856,6 +859,9 @@ defm "" : LMULWriteRes<"WriteVExtV", []>;
defm "" : LMULWriteRes<"WriteVICALUV", []>;
defm "" : LMULWriteRes<"WriteVICALUX", []>;
defm "" : LMULWriteRes<"WriteVICALUI", []>;
defm "" : LMULWriteRes<"WriteVICALUMV", []>;
defm "" : LMULWriteRes<"WriteVICALUMX", []>;
defm "" : LMULWriteRes<"WriteVICALUMI", []>;
defm "" : LMULWriteRes<"WriteVShiftV", []>;
defm "" : LMULWriteRes<"WriteVShiftX", []>;
defm "" : LMULWriteRes<"WriteVShiftI", []>;
Expand Down
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