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[llvm-exegesis] Add Pfm Counters for SapphireRapids #113847

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Merged
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Oct 28, 2024
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[llvm-exegesis] Add Pfm Counters for SapphireRapids #113847

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16 changes: 16 additions & 0 deletions llvm/lib/Target/X86/X86PfmCounters.td
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Original file line number Diff line number Diff line change
Expand Up @@ -220,6 +220,22 @@ def AlderLakePfmCounters : ProcPfmCounters {
}
def : PfmCountersBinding<"alderlake", AlderLakePfmCounters>;

def SapphireRapidsPfmCounters : ProcPfmCounters {
let CycleCounter = UnhaltedCoreCyclesPfmCounter;
let UopsCounter = UopsIssuedPfmCounter;
let IssueCounters = [
PfmIssueCounter<"SPRPort00", "uops_dispatched_port:port_0">,
PfmIssueCounter<"SPRPort01", "uops_dispatched_port:port_1">,
PfmIssueCounter<"SPRPort02_03_10", "uops_dispatched_port:port_2_3_10">,
PfmIssueCounter<"SPRPort04_09", "uops_dispatched_port:port_4_9">,
PfmIssueCounter<"SPRPort05_11", "uops_dispatched_port:port_5_11">,
PfmIssueCounter<"SPRPort06", "uops_dispatched_port:port_6">,
PfmIssueCounter<"SPRPort07_08", "uops_dispatched_port:port_7_8">,
];
let ValidationCounters = DefaultIntelPfmValidationCounters;
}
def : PfmCountersBinding<"sapphirerapids", SapphireRapidsPfmCounters>;

// AMD X86 Counters.
defvar DefaultAMDPfmValidationCounters = [
PfmValidationCounter<InstructionRetired, "RETIRED_INSTRUCTIONS">,
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6 changes: 6 additions & 0 deletions llvm/lib/Target/X86/X86SchedSapphireRapids.td
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Expand Up @@ -59,6 +59,8 @@ def SPRPort01_05 : ProcResGroup<[SPRPort01, SPRPort05]>;
def SPRPort01_05_10 : ProcResGroup<[SPRPort01, SPRPort05, SPRPort10]>;
def SPRPort02_03 : ProcResGroup<[SPRPort02, SPRPort03]>;
def SPRPort02_03_11 : ProcResGroup<[SPRPort02, SPRPort03, SPRPort11]>;
def SPRPort02_03_10 : ProcResGroup<[SPRPort02, SPRPort03, SPRPort10]>;
def SPRPort05_11 : ProcResGroup<[SPRPort05, SPRPort11]>;
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@HaohaiWen HaohaiWen Oct 28, 2024

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If I recall correctly, 2,3,11 is a group according to intel optimization manual. https://www.intel.com/content/www/us/en/content-details/814198/intel-64-and-ia-32-architectures-optimization-reference-manual-volume-1.html
uops.info and some website and even some intel tool made mistake to swap them.
I fixed this in https://reviews.llvm.org/D130897. llvm/utils/schedtool/tools/add_uops_uopsinfo.py:29 print('Warning: port 10 and port 11 are reversed on uops.info.', "Let's swap them.", file=sys.stderr)

image

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@HaohaiWen HaohaiWen Oct 28, 2024

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Ports should be based on optimization manual.

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@boomanaiden154 boomanaiden154 Oct 28, 2024

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Are we sure this isn't a typo in the optimization manual there? All of the other tools being different makes it seem like something might be up here.

I just took the names of the performance counters from libpfm, so it would probably need to be adjusted there too first.

def SPRPort07_08 : ProcResGroup<[SPRPort07, SPRPort08]>;

// EU has 112 reservation stations.
Expand All @@ -78,6 +80,10 @@ def SPRPort02_03_07_08_11 : ProcResGroup<[SPRPort02, SPRPort03, SPRPort07,
let BufferSize = 72;
}

def SPRPortAny : ProcResGroup<[SPRPort00, SPRPort01, SPRPort02, SPRPort03,
SPRPort04, SPRPort05, SPRPort06, SPRPort07,
SPRPort08, SPRPort09, SPRPort10, SPRPort11]>;

// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available
// until 5 cycles after the memory operand.
def : ReadAdvance<ReadAfterLd, 5>;
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