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[TableGen] Make !and and !or short-circuit #113963

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Merged
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Nov 7, 2024
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[TableGen] Make !and and !or short-circuit #113963

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425ddc6
[TableGen] Make `!and` short-circuit when either of the operand is zero
mshockwave Oct 28, 2024
8cce6ce
Add short-circuit for `!or` and add documentations
mshockwave Oct 30, 2024
b20cf29
Only short circuit against the left-most operand
mshockwave Nov 4, 2024
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17 changes: 17 additions & 0 deletions llvm/lib/TableGen/Record.cpp
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Expand Up @@ -1543,6 +1543,23 @@ const Init *BinOpInit::resolveReferences(Resolver &R) const {
const Init *lhs = LHS->resolveReferences(R);
const Init *rhs = RHS->resolveReferences(R);

if (getOpcode() == AND) {
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@jurahul jurahul Oct 28, 2024

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Do we need similar short circuit for OR as well?

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@mshockwave mshockwave Oct 29, 2024

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Good point, I had thought this before. The problem is that since !or is for both logical and bitwise operation, we can't short circuit something like this !or(true, <unknown / unresolved>) until the second operand is resolved (in which case it's not a short circuit anymore) because we're not sure if the second operand is a int (bitwise OR) or a bit (logical OR).

That said, I think a separate logical OR / AND like you suggested might help us to apply short-circuit with more confidence.

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@mshockwave mshockwave Oct 30, 2024

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Good point, I had thought this before. The problem is that since !or is for both logical and bitwise operation, we can't short circuit something like this !or(true, <unknown / unresolved>) until the second operand is resolved (in which case it's not a short circuit anymore) because we're not sure if the second operand is a int (bitwise OR) or a bit (logical OR).

I just made a blunder and forgot that !or(<all ones>, ...) can also be short-circuited. I'll add this case into this patch as well.

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@mshockwave mshockwave Oct 30, 2024

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The short-circuit for !or against all ones was just added.

// Short-circuit. Regardless whether this is a logical or bitwise
// AND.
if (lhs != LHS)
if (const auto *LHSi = dyn_cast_or_null<IntInit>(
lhs->convertInitializerTo(IntRecTy::get(getRecordKeeper())))) {
if (!LHSi->getValue())
return LHSi;
}
if (rhs != RHS)
if (const auto *RHSi = dyn_cast_or_null<IntInit>(
rhs->convertInitializerTo(IntRecTy::get(getRecordKeeper())))) {
if (!RHSi->getValue())
return RHSi;
}
}

if (LHS != lhs || RHS != rhs)
return (BinOpInit::get(getOpcode(), lhs, rhs, getType()))
->Fold(R.getCurrentRecord());
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14 changes: 14 additions & 0 deletions llvm/test/TableGen/true-false.td
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Expand Up @@ -67,6 +67,20 @@ def rec7 {
bits<3> flags = { true, false, true };
}

// The `!and` should be short-circuit such that `!tail` on empty list will never
// be evaluated.
// CHECK: def rec8
// CHECK: list<int> newSeq = [];
// CHECK: list<int> newSeq2 = [];

class Foo <list<int> seq = []> {
bit containsStr = !ne(!find(NAME, "BAR"), -1);
list<int> newSeq = !if(!and(!not(!empty(seq)), containsStr), !tail(seq), seq);
list<int> newSeq2 = !if(!and(containsStr, !not(!empty(seq))), !tail(seq), seq);
}

def rec8 : Foo<>;

#ifdef ERROR1
// ERROR1: Record name '1' is not a string

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