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[GlobalISel][AArch64] Legalize G_SPLAT_VECTOR #114006

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Oct 31, 2024
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[GlobalISel][AArch64] Legalize G_SPLAT_VECTOR #114006

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57f3103
[GlobalISel][AArch64] Legalize G_SPLAT_VECTOR
tschuett Oct 29, 2024
a6bf289
address review comments
tschuett Oct 29, 2024
bea4007
remove -debug
tschuett Oct 29, 2024
4dab4c4
extend comment
tschuett Oct 29, 2024
548a6b9
rebuild legalize splat vector test
tschuett Oct 30, 2024
b421a32
address review comments
tschuett Oct 31, 2024
eee26f8
fix tests
tschuett Oct 31, 2024
2763169
ping ci
tschuett Oct 31, 2024
f11cdbd
test ci
tschuett Oct 31, 2024
6098d91
test ci 2
tschuett Oct 31, 2024
35fc859
windows happy me unhapy
tschuett Oct 31, 2024
363e3ee
remove mir file
tschuett Oct 31, 2024
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1 change: 1 addition & 0 deletions llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
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Expand Up @@ -148,6 +148,7 @@ def : GINodeEquiv<G_INSERT_VECTOR_ELT, vector_insert>;
def : GINodeEquiv<G_CONCAT_VECTORS, concat_vectors>;
def : GINodeEquiv<G_BUILD_VECTOR, build_vector>;
def : GINodeEquiv<G_EXTRACT_SUBVECTOR, extract_subvector>;
def : GINodeEquiv<G_SPLAT_VECTOR, splat_vector>;
def : GINodeEquiv<G_FCEIL, fceil>;
def : GINodeEquiv<G_FCOS, fcos>;
def : GINodeEquiv<G_FSIN, fsin>;
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4 changes: 4 additions & 0 deletions llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
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Expand Up @@ -1316,6 +1316,10 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.widenScalarOrEltToNextPow2(0)
.immIdx(0); // Inform verifier imm idx 0 is handled.

// TODO: {nxv16s8, s8}, {nxv8s16, s16}
getActionDefinitionsBuilder(G_SPLAT_VECTOR)
.legalFor(HasSVE, {{nxv4s32, s32}, {nxv2s64, s64}});

getLegacyLegalizerInfo().computeTables();
verify(*ST.getInstrInfo());
}
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144 changes: 144 additions & 0 deletions llvm/test/CodeGen/AArch64/GlobalISel/legalize-splat-vector.mir
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@@ -0,0 +1,144 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=aarch64-apple-ios -mattr=+sve -aarch64-enable-gisel-sve=1 -global-isel -start-before=legalizer -stop-after=instruction-select %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SELECT
# RUN: llc -O0 -mtriple=aarch64-apple-ios -mattr=+sve -aarch64-enable-gisel-sve=1 -global-isel -start-before=legalizer -stop-after=regbankselect %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-REGBANK
# RUN: llc -O0 -mtriple=aarch64-apple-ios -mattr=+sve -aarch64-enable-gisel-sve=1 -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LEGAL

# REQUIRES: asserts, aarch64-registered-target

---
name: test_splat_vector_s64
body: |
bb.1:
; CHECK-SELECT-LABEL: name: test_splat_vector_s64
; CHECK-SELECT: %imm:gpr64sp = COPY $x0
; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_D %imm
; CHECK-SELECT-NEXT: $z0 = COPY %splat
;
; CHECK-REGBANK-LABEL: name: test_splat_vector_s64
; CHECK-REGBANK: %imm:gpr(s64) = COPY $x0
; CHECK-REGBANK-NEXT: %splat:fpr(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
; CHECK-REGBANK-NEXT: $z0 = COPY %splat(<vscale x 2 x s64>)
;
; CHECK-LEGAL-LABEL: name: test_splat_vector_s64
; CHECK-LEGAL: %imm:_(s64) = COPY $x0
; CHECK-LEGAL-NEXT: %splat:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
; CHECK-LEGAL-NEXT: $z0 = COPY %splat(<vscale x 2 x s64>)
%imm:_(s64) = COPY $x0
%splat:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
$z0 = COPY %splat(<vscale x 2 x s64>)
...
---
name: test_splat_vector_s64_const
body: |
bb.1:
; CHECK-SELECT-LABEL: name: test_splat_vector_s64_const
; CHECK-SELECT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 9
; CHECK-SELECT-NEXT: %imm:gpr64sp = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_D %imm
; CHECK-SELECT-NEXT: $z0 = COPY %splat
;
; CHECK-REGBANK-LABEL: name: test_splat_vector_s64_const
; CHECK-REGBANK: %imm:gpr(s64) = G_CONSTANT i64 9
; CHECK-REGBANK-NEXT: %splat:fpr(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
; CHECK-REGBANK-NEXT: $z0 = COPY %splat(<vscale x 2 x s64>)
;
; CHECK-LEGAL-LABEL: name: test_splat_vector_s64_const
; CHECK-LEGAL: %imm:_(s64) = G_CONSTANT i64 9
; CHECK-LEGAL-NEXT: %splat:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
; CHECK-LEGAL-NEXT: $z0 = COPY %splat(<vscale x 2 x s64>)
%imm:_(s64) = G_CONSTANT i64 9
%splat:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
$z0 = COPY %splat(<vscale x 2 x s64>)
...
---
name: test_splat_vector_s64_fconst
body: |
bb.1:
; CHECK-SELECT-LABEL: name: test_splat_vector_s64_fconst
; CHECK-SELECT: %imm:fpr64 = FMOVDi 34
; CHECK-SELECT-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY %imm
; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_D [[COPY]]
; CHECK-SELECT-NEXT: $z0 = COPY %splat
;
; CHECK-REGBANK-LABEL: name: test_splat_vector_s64_fconst
; CHECK-REGBANK: %imm:fpr(s64) = G_FCONSTANT double 9.000000e+00
; CHECK-REGBANK-NEXT: [[COPY:%[0-9]+]]:gpr(s64) = COPY %imm(s64)
; CHECK-REGBANK-NEXT: %splat:fpr(<vscale x 2 x s64>) = G_SPLAT_VECTOR [[COPY]](s64)
; CHECK-REGBANK-NEXT: $z0 = COPY %splat(<vscale x 2 x s64>)
;
; CHECK-LEGAL-LABEL: name: test_splat_vector_s64_fconst
; CHECK-LEGAL: %imm:_(s64) = G_FCONSTANT double 9.000000e+00
; CHECK-LEGAL-NEXT: %splat:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
; CHECK-LEGAL-NEXT: $z0 = COPY %splat(<vscale x 2 x s64>)
%imm:_(s64) = G_FCONSTANT double 9.0
%splat:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %imm(s64)
$z0 = COPY %splat(<vscale x 2 x s64>)
...
---
name: test_splat_vector_s32
body: |
bb.1:
; CHECK-SELECT-LABEL: name: test_splat_vector_s32
; CHECK-SELECT: %imm:gpr32sp = COPY $w0
; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_S %imm
; CHECK-SELECT-NEXT: $z0 = COPY %splat
;
; CHECK-REGBANK-LABEL: name: test_splat_vector_s32
; CHECK-REGBANK: %imm:gpr(s32) = COPY $w0
; CHECK-REGBANK-NEXT: %splat:fpr(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
; CHECK-REGBANK-NEXT: $z0 = COPY %splat(<vscale x 4 x s32>)
;
; CHECK-LEGAL-LABEL: name: test_splat_vector_s32
; CHECK-LEGAL: %imm:_(s32) = COPY $w0
; CHECK-LEGAL-NEXT: %splat:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
; CHECK-LEGAL-NEXT: $z0 = COPY %splat(<vscale x 4 x s32>)
%imm:_(s32) = COPY $w0
%splat:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
$z0 = COPY %splat(<vscale x 4 x s32>)
...
---
name: test_splat_vector_s32_const
body: |
bb.1:
; CHECK-SELECT-LABEL: name: test_splat_vector_s32_const
; CHECK-SELECT: %imm:gpr32common = MOVi32imm 9
; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_S %imm
; CHECK-SELECT-NEXT: $z0 = COPY %splat
;
; CHECK-REGBANK-LABEL: name: test_splat_vector_s32_const
; CHECK-REGBANK: %imm:gpr(s32) = G_CONSTANT i32 9
; CHECK-REGBANK-NEXT: %splat:fpr(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
; CHECK-REGBANK-NEXT: $z0 = COPY %splat(<vscale x 4 x s32>)
;
; CHECK-LEGAL-LABEL: name: test_splat_vector_s32_const
; CHECK-LEGAL: %imm:_(s32) = G_CONSTANT i32 9
; CHECK-LEGAL-NEXT: %splat:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
; CHECK-LEGAL-NEXT: $z0 = COPY %splat(<vscale x 4 x s32>)
%imm:_(s32) = G_CONSTANT i32 9
%splat:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
$z0 = COPY %splat(<vscale x 4 x s32>)
...
---
name: test_splat_vector_s32_fconst
body: |
bb.1:
; CHECK-SELECT-LABEL: name: test_splat_vector_s32_fconst
; CHECK-SELECT: %imm:fpr32 = FMOVSi 28
; CHECK-SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY %imm
; CHECK-SELECT-NEXT: %splat:zpr = DUP_ZR_S [[COPY]]
; CHECK-SELECT-NEXT: $z0 = COPY %splat
;
; CHECK-REGBANK-LABEL: name: test_splat_vector_s32_fconst
; CHECK-REGBANK: %imm:fpr(s32) = G_FCONSTANT float 7.000000e+00
; CHECK-REGBANK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %imm(s32)
; CHECK-REGBANK-NEXT: %splat:fpr(<vscale x 4 x s32>) = G_SPLAT_VECTOR [[COPY]](s32)
; CHECK-REGBANK-NEXT: $z0 = COPY %splat(<vscale x 4 x s32>)
;
; CHECK-LEGAL-LABEL: name: test_splat_vector_s32_fconst
; CHECK-LEGAL: %imm:_(s32) = G_FCONSTANT float 7.000000e+00
; CHECK-LEGAL-NEXT: %splat:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
; CHECK-LEGAL-NEXT: $z0 = COPY %splat(<vscale x 4 x s32>)
%imm:_(s32) = G_FCONSTANT float 7.0
%splat:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %imm(s32)
$z0 = COPY %splat(<vscale x 4 x s32>)
...
73 changes: 73 additions & 0 deletions llvm/test/CodeGen/AArch64/GlobalISel/select-splat-vector.ll
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@@ -0,0 +1,73 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc < %s -mtriple aarch64 -mattr=+sve -aarch64-enable-gisel-sve=1 | FileCheck %s --check-prefixes=CHECK,CHECK-SDAG
; RUN: llc < %s -mtriple aarch64 -mattr=+sve -global-isel -aarch64-enable-gisel-sve=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GS

; REQUIRES: asserts, aarch64-registered-target

;; add
define <vscale x 2 x i64> @addnxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
; CHECK-SDAG-LABEL: addnxv2i64:
; CHECK-SDAG: // %bb.0: // %entry
; CHECK-SDAG-NEXT: add z0.d, z0.d, #9 // =0x9
; CHECK-SDAG-NEXT: ret
;
; CHECK-GS-LABEL: addnxv2i64:
; CHECK-GS: // %bb.0: // %entry
; CHECK-GS-NEXT: mov w8, #9 // =0x9
; CHECK-GS-NEXT: mov z1.d, x8
; CHECK-GS-NEXT: add z0.d, z0.d, z1.d
; CHECK-GS-NEXT: ret
entry:
%c = add <vscale x 2 x i64> %a, splat (i64 9)
ret <vscale x 2 x i64> %c
}

define <vscale x 2 x i64> @splarnxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
; CHECK-SDAG-LABEL: splarnxv2i64:
; CHECK-SDAG: // %bb.0: // %entry
; CHECK-SDAG-NEXT: mov z0.d, #9 // =0x9
; CHECK-SDAG-NEXT: ret
;
; CHECK-GS-LABEL: splarnxv2i64:
; CHECK-GS: // %bb.0: // %entry
; CHECK-GS-NEXT: mov w8, #9 // =0x9
; CHECK-GS-NEXT: mov z0.d, x8
; CHECK-GS-NEXT: ret
entry:
ret <vscale x 2 x i64> splat (i64 9)
}

define <vscale x 4 x i32> @addnxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
; CHECK-SDAG-LABEL: addnxv4i32:
; CHECK-SDAG: // %bb.0: // %entry
; CHECK-SDAG-NEXT: add z0.s, z0.s, #9 // =0x9
; CHECK-SDAG-NEXT: ret
;
; CHECK-GS-LABEL: addnxv4i32:
; CHECK-GS: // %bb.0: // %entry
; CHECK-GS-NEXT: mov w8, #9 // =0x9
; CHECK-GS-NEXT: mov z1.s, w8
; CHECK-GS-NEXT: add z0.s, z0.s, z1.s
; CHECK-GS-NEXT: ret
entry:
%c = add <vscale x 4 x i32> %a, splat (i32 9)
ret <vscale x 4 x i32> %c
}

define <vscale x 4 x i32> @splatnxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
; CHECK-SDAG-LABEL: splatnxv4i32:
; CHECK-SDAG: // %bb.0: // %entry
; CHECK-SDAG-NEXT: mov z0.s, #9 // =0x9
; CHECK-SDAG-NEXT: ret
;
; CHECK-GS-LABEL: splatnxv4i32:
; CHECK-GS: // %bb.0: // %entry
; CHECK-GS-NEXT: mov w8, #9 // =0x9
; CHECK-GS-NEXT: mov z0.s, w8
; CHECK-GS-NEXT: ret
entry:
ret <vscale x 4 x i32> splat (i32 9)
}

;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK: {{.*}}