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[AArch64][SVE] Use INS when moving elements from bottom 128b of SVE type #114034

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Merged
merged 4 commits into from
Oct 31, 2024
Merged

[AArch64][SVE] Use INS when moving elements from bottom 128b of SVE type #114034

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5fce5b4
[AArch64][SVE] Use INS when moving elements from bottom 128b of SVE type
SpencerAbson Oct 29, 2024
2d6e6df
Merge new patterns into existing Neon_INS_elt_patterns work
SpencerAbson Oct 29, 2024
c357f65
simplify implementation of new patterns
SpencerAbson Oct 30, 2024
4f236b0
Restore ordering of pattern defs
SpencerAbson Oct 31, 2024
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35 changes: 25 additions & 10 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -7222,8 +7222,23 @@ def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane
V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
)>;

multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
ValueType VTScal, Instruction INS> {
// Move elements between vectors
multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64, ValueType VTSVE,
ValueType VTScal, Operand SVEIdxTy, Instruction INS> {
// Extracting from the lowest 128-bits of an SVE vector
def : Pat<(VT128 (vector_insert VT128:$Rn,
(VTScal (vector_extract VTSVE:$Rm, (i64 SVEIdxTy:$Immn))),
(i64 imm:$Immd))),
(INS VT128:$Rn, imm:$Immd, (VT128 (EXTRACT_SUBREG VTSVE:$Rm, zsub)), SVEIdxTy:$Immn)>;

def : Pat<(VT64 (vector_insert VT64:$Rn,
(VTScal (vector_extract VTSVE:$Rm, (i64 SVEIdxTy:$Immn))),
(i64 imm:$Immd))),
(EXTRACT_SUBREG
(INS (SUBREG_TO_REG (i64 0), VT64:$Rn, dsub), imm:$Immd,
(VT128 (EXTRACT_SUBREG VTSVE:$Rm, zsub)), SVEIdxTy:$Immn),
dsub)>;
// Extracting from another NEON vector
def : Pat<(VT128 (vector_insert V128:$src,
(VTScal (vector_extract (VT128 V128:$Rn), (i64 imm:$Immn))),
(i64 imm:$Immd))),
Expand Down Expand Up @@ -7251,15 +7266,15 @@ multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
dsub)>;
}

defm : Neon_INS_elt_pattern<v8f16, v4f16, f16, INSvi16lane>;
defm : Neon_INS_elt_pattern<v8bf16, v4bf16, bf16, INSvi16lane>;
defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>;
defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
defm : Neon_INS_elt_pattern<v8f16, v4f16, nxv8f16, f16, VectorIndexH, INSvi16lane>;
defm : Neon_INS_elt_pattern<v8bf16, v4bf16, nxv8bf16, bf16, VectorIndexH, INSvi16lane>;
defm : Neon_INS_elt_pattern<v4f32, v2f32, nxv4f32, f32, VectorIndexS, INSvi32lane>;
defm : Neon_INS_elt_pattern<v2f64, v1f64, nxv2f64, f64, VectorIndexD, INSvi64lane>;

defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, INSvi8lane>;
defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, INSvi16lane>;
defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, INSvi32lane>;
defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, INSvi64lane>;
defm : Neon_INS_elt_pattern<v16i8, v8i8, nxv16i8, i32, VectorIndexB, INSvi8lane>;
defm : Neon_INS_elt_pattern<v8i16, v4i16, nxv8i16, i32, VectorIndexH, INSvi16lane>;
defm : Neon_INS_elt_pattern<v4i32, v2i32, nxv4i32, i32, VectorIndexS, INSvi32lane>;
defm : Neon_INS_elt_pattern<v2i64, v1i64, nxv2i64, i64, VectorIndexD, INSvi64lane>;

// Insert from bitcast
// vector_insert(bitcast(f32 src), n, lane) -> INSvi32lane(src, lane, INSERT_SUBREG(-, n), 0)
Expand Down
15 changes: 15 additions & 0 deletions llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -3365,6 +3365,21 @@ let Predicates = [HasSVEorSME] in {
(UMOVvi32 (v4i32 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexS:$index)>;
def : Pat<(i64 (vector_extract nxv2i64:$vec, VectorIndexD:$index)),
(UMOVvi64 (v2i64 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexD:$index)>;

// Move element from the bottom 128-bits of a scalable vector to a single-element vector.
// Alternative case where insertelement is just scalar_to_vector rather than vector_insert.
def : Pat<(v1f64 (scalar_to_vector
(f64 (vector_extract nxv2f64:$vec, VectorIndexD:$index)))),
(EXTRACT_SUBREG
(INSvi64lane (IMPLICIT_DEF), (i64 0),
(EXTRACT_SUBREG nxv2f64:$vec, zsub), VectorIndexD:$index),
dsub)>;
def : Pat<(v1i64 (scalar_to_vector
(i64 (vector_extract nxv2i64:$vec, VectorIndexD:$index)))),
(EXTRACT_SUBREG
(INSvi64lane (IMPLICIT_DEF), (i64 0),
(EXTRACT_SUBREG nxv2i64:$vec, zsub), VectorIndexD:$index),
dsub)>;
} // End HasNEON

let Predicates = [HasNEON] in {
Expand Down
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