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[RISCV] Add OperandType for sew and vecpolicy operands. #114168

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Merged
merged 3 commits into from
Oct 30, 2024
Merged

[RISCV] Add OperandType for sew and vecpolicy operands. #114168

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b5303f6
[RISCV] Add OperandType for sew and vecpolicy operands.
topperc Oct 30, 2024
dcbb655
fixup! rename vecpolicy -> vec_policy.
topperc Oct 30, 2024
9948a6e
Merge remote-tracking branch 'origin/main' into pr/sew-vecpolicy
topperc Oct 30, 2024
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6 changes: 5 additions & 1 deletion llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -337,7 +337,11 @@ enum OperandType : unsigned {
OPERAND_RTZARG,
// Condition code used by select and short forward branch pseudos.
OPERAND_COND_CODE,
OPERAND_LAST_RISCV_IMM = OPERAND_COND_CODE,
// Vector policy operand.
OPERAND_VEC_POLICY,
// Vector SEW operand.
OPERAND_SEW,
OPERAND_LAST_RISCV_IMM = OPERAND_SEW,
// Operand is either a register or uimm5, this is used by V extension pseudo
// instructions to represent a value that be passed as AVL to either vsetvli
// or vsetivli.
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6 changes: 6 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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Expand Up @@ -2545,6 +2545,12 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
case RISCVOp::OPERAND_COND_CODE:
Ok = Imm >= 0 && Imm < RISCVCC::COND_INVALID;
break;
case RISCVOp::OPERAND_VEC_POLICY:
Ok = (Imm & (RISCVII::TAIL_AGNOSTIC | RISCVII::MASK_AGNOSTIC)) == Imm;
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@dtcxzyw dtcxzyw Oct 30, 2024

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Can be simplified to Imm <= (RISCVII::TAIL_AGNOSTIC | RISCVII::MASK_AGNOSTIC).

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@dtcxzyw dtcxzyw Oct 30, 2024

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Oops, it is a signed integer :(

break;
case RISCVOp::OPERAND_SEW:
Ok = Imm == 0 || (Imm >= 3 && Imm <= 6);
break;
}
if (!Ok) {
ErrInfo = "Invalid immediate";
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