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[AArch64] Create set.fpmr intrinsic and assembly lowering #114248

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Merged
merged 3 commits into from
Nov 8, 2024
Merged

[AArch64] Create set.fpmr intrinsic and assembly lowering #114248

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b9e8362
[AArch64] Create set.fpmr intrinsic and assembly lowering
Lukacma Oct 30, 2024
4ee6072
switch to using simple msr and address comments
Lukacma Nov 5, 2024
4851feb
fix incorrect defs and refactor code
Lukacma Nov 5, 2024
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3 changes: 3 additions & 0 deletions llvm/include/llvm/IR/IntrinsicsAArch64.td
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Original file line number Diff line number Diff line change
Expand Up @@ -778,6 +778,9 @@ def int_aarch64_get_fpcr : FPENV_Get_Intrinsic;
def int_aarch64_set_fpcr : FPENV_Set_Intrinsic;
def int_aarch64_get_fpsr : FPENV_Get_Intrinsic;
def int_aarch64_set_fpsr : FPENV_Set_Intrinsic;
def int_aarch64_set_fpmr : DefaultAttrsIntrinsic<[], [llvm_i64_ty], [IntrInaccessibleMemOnly]>{
let TargetPrefix = "aarch64";
}

// Armv8.5-A Random number generation intrinsics
def int_aarch64_rndr : RNDR_Intrinsic;
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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/LivePhysRegs.cpp
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Expand Up @@ -262,7 +262,7 @@ void llvm::addLiveIns(MachineBasicBlock &MBB, const LivePhysRegs &LiveRegs) {
const MachineRegisterInfo &MRI = MF.getRegInfo();
const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
for (MCPhysReg Reg : LiveRegs) {
if (MRI.isReserved(Reg))
if (TRI.getReservedRegs(MF).test(Reg))
continue;
// Skip the register if we are about to add one of its super registers.
if (any_of(TRI.superregs(Reg), [&](MCPhysReg SReg) {
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6 changes: 6 additions & 0 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.td
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Expand Up @@ -2145,6 +2145,12 @@ def MSR_FPSR : Pseudo<(outs), (ins GPR64:$val),
PseudoInstExpansion<(MSR 0xda21, GPR64:$val)>,
Sched<[WriteSys]>;

let Uses = [FPMR], Defs = [FPMR, NZCV] in
def SET_FPMR : Pseudo<(outs), (ins GPR64:$val),
[(int_aarch64_set_fpmr i64:$val)]>,
PseudoInstExpansion<(MSR 0xda22, GPR64:$val)>,
Sched<[WriteSys]>;

// Generic system instructions
def SYSxt : SystemXtI<0, "sys">;
def SYSLxt : SystemLXtI<1, "sysl">;
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11 changes: 10 additions & 1 deletion llvm/test/CodeGen/AArch64/arm64-fpenv.ll
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@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64 -verify-machineinstrs < %s | FileCheck %s

define i64 @get_fpcr() #0 {
; CHECK-LABEL: get_fpcr:
Expand Down Expand Up @@ -37,6 +37,15 @@ define void @set_fpsr(i64 %sr) {
ret void
}

define void @set_fpmr(i64 %sr) {
; CHECK-LABEL: set_fpmr:
; CHECK: // %bb.0:
; CHECK-NEXT: msr FPMR, x0
; CHECK-NEXT: ret
call void @llvm.aarch64.set.fpmr(i64 %sr)
ret void
}

declare i64 @llvm.aarch64.get.fpcr()
declare void @llvm.aarch64.set.fpcr(i64)
declare i64 @llvm.aarch64.get.fpsr()
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