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[RISCV] Add hasPostISelHook to sf.vfnrclip pseudo instructions. #114274

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Merged
merged 5 commits into from
Oct 30, 2024
Merged

[RISCV] Add hasPostISelHook to sf.vfnrclip pseudo instructions. #114274

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4827265
[RISCV] Add missing hasPostISelHook = 1 to vector pseudos that might …
topperc Oct 30, 2024
6c7ec35
Merge remote-tracking branch 'origin/main' into pr/rounding-post-isel
topperc Oct 30, 2024
529a555
Merge remote-tracking branch 'origin/main' into pr/rounding-mode-sink
topperc Oct 30, 2024
4b83ebc
[RISCV] Add hasPostISelHook to sf.vfnrclip pseudo instructions.
topperc Oct 30, 2024
de57e89
Merge remote-tracking branch 'origin/main' into pr/vfnrclip
topperc Oct 30, 2024
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5 changes: 3 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
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Original file line number Diff line number Diff line change
Expand Up @@ -222,7 +222,8 @@ let Predicates = [HasVendorXSfvfwmaccqqq], DecoderNamespace = "XSfvfwmaccqqq",
def VFWMACC_4x4x4 : CustomSiFiveVMACC<0b111100, OPFVV, "sf.vfwmacc.4x4x4">;
}

let Predicates = [HasVendorXSfvfnrclipxfqf], DecoderNamespace = "XSfvfnrclipxfqf" in {
let Predicates = [HasVendorXSfvfnrclipxfqf], DecoderNamespace = "XSfvfnrclipxfqf",
Uses = [FRM] in {
def VFNRCLIP_XU_F_QF : CustomSiFiveVFNRCLIP<0b100010, OPFVF, "sf.vfnrclip.xu.f.qf">;
def VFNRCLIP_X_F_QF : CustomSiFiveVFNRCLIP<0b100011, OPFVF, "sf.vfnrclip.x.f.qf">;
}
Expand Down Expand Up @@ -405,7 +406,7 @@ multiclass VPseudoSiFiveVFWMACC<string Constraint = ""> {

multiclass VPseudoSiFiveVFNRCLIP<string Constraint = "@earlyclobber $rd"> {
foreach i = 0-4 in
let hasSideEffects = 0 in
let hasSideEffects = 0, hasPostISelHook = 1 in
defm "Pseudo" # NAME : VPseudoBinaryRoundingMode<MxListW[i].vrclass,
MxListVF4[i].vrclass,
FPR32, MxListW[i],
Expand Down
4 changes: 1 addition & 3 deletions llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll
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Expand Up @@ -13,18 +13,16 @@ declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.iXLen(
define <vscale x 1 x i8> @intrinsic_sf_vfnrclip_x_f_qf_nxv1i8_nxv1f32(<vscale x 1 x float> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_sf_vfnrclip_x_f_qf_nxv1i8_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fsrmi a1, 0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: sf.vfnrclip.x.f.qf v9, v8, fa0
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.iXLen(
<vscale x 1 x i8> undef,
<vscale x 1 x float> %0,
float %1,
iXLen 0, iXLen %2)
iXLen 7, iXLen %2)

ret <vscale x 1 x i8> %a
}
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4 changes: 1 addition & 3 deletions llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll
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Expand Up @@ -13,18 +13,16 @@ declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.iXLen(
define <vscale x 1 x i8> @intrinsic_sf_vfnrclip_xu_f_qf_nxv1i8_nxv1f32(<vscale x 1 x float> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_nxv1i8_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fsrmi a1, 0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: sf.vfnrclip.xu.f.qf v9, v8, fa0
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.iXLen(
<vscale x 1 x i8> undef,
<vscale x 1 x float> %0,
float %1,
iXLen 0, iXLen %2)
iXLen 7, iXLen %2)

ret <vscale x 1 x i8> %a
}
Expand Down
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