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2 changes: 1 addition & 1 deletion llvm/lib/Target/X86/X86ISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -49321,7 +49321,7 @@ static SDValue combineVectorShiftImm(SDNode *N, SelectionDAG &DAG,
if (!LogicalShift && ISD::isBuildVectorAllOnes(N0.getNode()))
// N0 is all ones or undef. We guarantee that the bits shifted into the
// result are all ones, not undef.
return DAG.getConstant(-1, SDLoc(N), VT);
return DAG.getAllOnesConstant(SDLoc(N), VT);

auto MergeShifts = [&](SDValue X, uint64_t Amt0, uint64_t Amt1) {
unsigned NewShiftVal = Amt0 + Amt1;
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