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[RISCV] Remove RISCVISD::VFCVT_X(U)_F_VL by using VFCVT_RM_X(U)_F_VL with DYN rounding mode. NFC #114306

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Merged
merged 7 commits into from
Oct 31, 2024
Merged

[RISCV] Remove RISCVISD::VFCVT_X(U)_F_VL by using VFCVT_RM_X(U)_F_VL with DYN rounding mode. NFC #114306

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4827265
[RISCV] Add missing hasPostISelHook = 1 to vector pseudos that might …
topperc Oct 30, 2024
6c7ec35
Merge remote-tracking branch 'origin/main' into pr/rounding-post-isel
topperc Oct 30, 2024
529a555
Merge remote-tracking branch 'origin/main' into pr/rounding-mode-sink
topperc Oct 30, 2024
15f5144
[RISCV] Remove duplicate vector conversion pseudos.
topperc Oct 30, 2024
744bbe0
Merge remote-tracking branch 'origin/main' into pr/redundant-pseudos
topperc Oct 30, 2024
3ea90bc
[RISCV] Remove VFCVT_X(U)_F_VL by using VFCVT_RM_X(U)_F_VL with DYN r…
topperc Oct 30, 2024
806418f
Merge remote-tracking branch 'origin/main' into pr/merge-isd
topperc Oct 30, 2024
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30 changes: 15 additions & 15 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3030,6 +3030,7 @@ static RISCVFPRndMode::RoundingMode matchRoundingOp(unsigned Opc) {
case ISD::VP_FROUND:
return RISCVFPRndMode::RMM;
case ISD::FRINT:
case ISD::VP_FRINT:
return RISCVFPRndMode::DYN;
}

Expand Down Expand Up @@ -3101,6 +3102,8 @@ lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(SDValue Op, SelectionDAG &DAG,
switch (Op.getOpcode()) {
default:
llvm_unreachable("Unexpected opcode");
case ISD::FRINT:
case ISD::VP_FRINT:
case ISD::FCEIL:
case ISD::VP_FCEIL:
case ISD::FFLOOR:
Expand All @@ -3120,10 +3123,6 @@ lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(SDValue Op, SelectionDAG &DAG,
Truncated = DAG.getNode(RISCVISD::VFCVT_RTZ_X_F_VL, DL, IntVT, Src,
Mask, VL);
break;
case ISD::FRINT:
case ISD::VP_FRINT:
Truncated = DAG.getNode(RISCVISD::VFCVT_X_F_VL, DL, IntVT, Src, Mask, VL);
break;
case ISD::FNEARBYINT:
case ISD::VP_FNEARBYINT:
Truncated = DAG.getNode(RISCVISD::VFROUND_NOEXCEPT_VL, DL, ContainerVT, Src,
Expand Down Expand Up @@ -3294,8 +3293,10 @@ static SDValue lowerVectorXRINT(SDValue Op, SelectionDAG &DAG,
}

auto [Mask, VL] = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
SDValue Truncated =
DAG.getNode(RISCVISD::VFCVT_X_F_VL, DL, ContainerVT, Src, Mask, VL);
SDValue Truncated = DAG.getNode(
RISCVISD::VFCVT_RM_X_F_VL, DL, ContainerVT, Src, Mask,
DAG.getTargetConstant(RISCVFPRndMode::DYN, DL, Subtarget.getXLenVT()),
VL);

if (!VT.isFixedLengthVector())
return Truncated;
Expand Down Expand Up @@ -6170,7 +6171,7 @@ static unsigned getRISCVVLOp(SDValue Op) {
case ISD::VP_LRINT:
case ISD::LLRINT:
case ISD::VP_LLRINT:
return RISCVISD::VFCVT_X_F_VL;
return RISCVISD::VFCVT_RM_X_F_VL;
}
// clang-format on
#undef OP_CASE
Expand All @@ -6183,7 +6184,7 @@ static bool hasPassthruOp(unsigned Opcode) {
Opcode <= RISCVISD::LAST_RISCV_STRICTFP_OPCODE &&
"not a RISC-V target specific op");
static_assert(RISCVISD::LAST_VL_VECTOR_OP - RISCVISD::FIRST_VL_VECTOR_OP ==
130 &&
128 &&
RISCVISD::LAST_RISCV_STRICTFP_OPCODE -
ISD::FIRST_TARGET_STRICTFP_OPCODE ==
21 &&
Expand All @@ -6209,7 +6210,7 @@ static bool hasMaskOp(unsigned Opcode) {
Opcode <= RISCVISD::LAST_RISCV_STRICTFP_OPCODE &&
"not a RISC-V target specific op");
static_assert(RISCVISD::LAST_VL_VECTOR_OP - RISCVISD::FIRST_VL_VECTOR_OP ==
130 &&
128 &&
RISCVISD::LAST_RISCV_STRICTFP_OPCODE -
ISD::FIRST_TARGET_STRICTFP_OPCODE ==
21 &&
Expand Down Expand Up @@ -11549,6 +11550,11 @@ SDValue RISCVTargetLowering::lowerVPOp(SDValue Op, SelectionDAG &DAG) const {
}
}
}
// VFCVT_RM_X_F_VL requires a rounding mode to be injected before the VL.
if (RISCVISDOpc == RISCVISD::VFCVT_RM_X_F_VL &&
ISD::getVPExplicitVectorLengthIdx(Op.getOpcode()) == OpIdx.index())
Ops.push_back(DAG.getTargetConstant(RISCVFPRndMode::DYN, DL,
Subtarget.getXLenVT()));
// Pass through operands which aren't fixed-length vectors.
if (!V.getValueType().isFixedLengthVector()) {
Ops.push_back(V);
Expand Down Expand Up @@ -15710,10 +15716,6 @@ static SDValue performFP_TO_INTCombine(SDNode *N,
unsigned Opc =
IsSigned ? RISCVISD::VFCVT_RTZ_X_F_VL : RISCVISD::VFCVT_RTZ_XU_F_VL;
FpToInt = DAG.getNode(Opc, DL, ContainerVT, XVal, Mask, VL);
} else if (FRM == RISCVFPRndMode::DYN) {
unsigned Opc =
IsSigned ? RISCVISD::VFCVT_X_F_VL : RISCVISD::VFCVT_XU_F_VL;
FpToInt = DAG.getNode(Opc, DL, ContainerVT, XVal, Mask, VL);
} else {
unsigned Opc =
IsSigned ? RISCVISD::VFCVT_RM_X_F_VL : RISCVISD::VFCVT_RM_XU_F_VL;
Expand Down Expand Up @@ -20277,8 +20279,6 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
NODE_NAME_CASE(VFCVT_RTZ_XU_F_VL)
NODE_NAME_CASE(VFCVT_RM_X_F_VL)
NODE_NAME_CASE(VFCVT_RM_XU_F_VL)
NODE_NAME_CASE(VFCVT_X_F_VL)
NODE_NAME_CASE(VFCVT_XU_F_VL)
NODE_NAME_CASE(VFROUND_NOEXCEPT_VL)
NODE_NAME_CASE(SINT_TO_FP_VL)
NODE_NAME_CASE(UINT_TO_FP_VL)
Expand Down
2 changes: 0 additions & 2 deletions llvm/lib/Target/RISCV/RISCVISelLowering.h
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Original file line number Diff line number Diff line change
Expand Up @@ -307,8 +307,6 @@ enum NodeType : unsigned {
FCOPYSIGN_VL, // Has a passthru operand
VFCVT_RTZ_X_F_VL,
VFCVT_RTZ_XU_F_VL,
VFCVT_X_F_VL,
VFCVT_XU_F_VL,
VFROUND_NOEXCEPT_VL,
VFCVT_RM_X_F_VL, // Has a rounding mode operand.
VFCVT_RM_XU_F_VL, // Has a rounding mode operand.
Expand Down
67 changes: 0 additions & 67 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
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Original file line number Diff line number Diff line change
Expand Up @@ -270,8 +270,6 @@ def SDT_RISCVSETCCOP_VL : SDTypeProfile<1, 6, [
SDTCisSameAs<0, 5>, SDTCisVT<6, XLenVT>]>;

// Float -> Int
def riscv_vfcvt_xu_f_vl : SDNode<"RISCVISD::VFCVT_XU_F_VL", SDT_RISCVFP2IOp_VL>;
def riscv_vfcvt_x_f_vl : SDNode<"RISCVISD::VFCVT_X_F_VL", SDT_RISCVFP2IOp_VL>;
def riscv_vfcvt_rm_xu_f_vl : SDNode<"RISCVISD::VFCVT_RM_XU_F_VL", SDT_RISCVFP2IOp_RM_VL>;
def riscv_vfcvt_rm_x_f_vl : SDNode<"RISCVISD::VFCVT_RM_X_F_VL", SDT_RISCVFP2IOp_RM_VL>;

Expand Down Expand Up @@ -1206,24 +1204,6 @@ multiclass VPatConvertFP2IVL_V<SDPatternOperator vop, string instruction_name> {
}
}

multiclass VPatConvertFP2IVL_V_RM<SDPatternOperator vop, string instruction_name> {
foreach fvti = AllFloatVectors in {
defvar ivti = GetIntVTypeInfo<fvti>.Vti;
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
GetVTypePredicates<ivti>.Predicates) in
def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),
(fvti.Mask V0),
VLOpFrag)),
(!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_MASK")
(ivti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1,
(fvti.Mask V0),
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
GPR:$vl, ivti.Log2SEW, TA_MA)>;
}
}


multiclass VPatConvertFP2I_RM_VL_V<SDPatternOperator vop, string instruction_name> {
foreach fvti = AllFloatVectors in {
Expand Down Expand Up @@ -1289,25 +1269,6 @@ multiclass VPatWConvertFP2IVL_V<SDPatternOperator vop, string instruction_name>
}
}

multiclass VPatWConvertFP2IVL_V_RM<SDPatternOperator vop, string instruction_name> {
foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
GetVTypePredicates<iwti>.Predicates) in
def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),
(fvti.Mask V0),
VLOpFrag)),
(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK")
(iwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1,
(fvti.Mask V0),
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
GPR:$vl, fvti.Log2SEW, TA_MA)>;
}
}


multiclass VPatWConvertFP2I_RM_VL_V<SDNode vop, string instruction_name> {
foreach fvtiToFWti = AllWidenableFloatVectors in {
Expand Down Expand Up @@ -1361,28 +1322,6 @@ multiclass VPatNConvertFP2IVL_W<SDPatternOperator vop,
}
}

multiclass VPatNConvertFP2IVL_W_RM<SDPatternOperator vop,
string instruction_name> {
// Reuse the same list of types used in the widening nodes, but just swap the
// direction of types around so we're converting from Wti -> Vti
foreach vtiToWti = AllWidenableIntToFloatVectors in {
defvar vti = vtiToWti.Vti;
defvar fwti = vtiToWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<fwti>.Predicates) in
def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1),
(fwti.Mask V0),
VLOpFrag)),
(!cast<Instruction>(instruction_name#"_"#vti.LMul.MX#"_MASK")
(vti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1,
(fwti.Mask V0),
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
GPR:$vl, vti.Log2SEW, TA_MA)>;
}
}

multiclass VPatNConvertFP2I_RM_VL_W<SDNode vop, string instruction_name> {
foreach vtiToWti = AllWidenableIntToFloatVectors in {
defvar vti = vtiToWti.Vti;
Expand Down Expand Up @@ -2637,8 +2576,6 @@ foreach fvti = AllFloatVectors in {
}

// 13.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions
defm : VPatConvertFP2IVL_V_RM<riscv_vfcvt_xu_f_vl, "PseudoVFCVT_XU_F_V">;
defm : VPatConvertFP2IVL_V_RM<riscv_vfcvt_x_f_vl, "PseudoVFCVT_X_F_V">;
defm : VPatConvertFP2I_RM_VL_V<riscv_vfcvt_rm_xu_f_vl, "PseudoVFCVT_XU_F_V">;
defm : VPatConvertFP2I_RM_VL_V<any_riscv_vfcvt_rm_x_f_vl, "PseudoVFCVT_X_F_V">;

Expand All @@ -2652,8 +2589,6 @@ defm : VPatConvertI2FP_RM_VL_V<riscv_vfcvt_rm_f_xu_vl, "PseudoVFCVT_F_XU_V">;
defm : VPatConvertI2FP_RM_VL_V<riscv_vfcvt_rm_f_x_vl, "PseudoVFCVT_F_X_V">;

// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
defm : VPatWConvertFP2IVL_V_RM<riscv_vfcvt_xu_f_vl, "PseudoVFWCVT_XU_F_V">;
defm : VPatWConvertFP2IVL_V_RM<riscv_vfcvt_x_f_vl, "PseudoVFWCVT_X_F_V">;
defm : VPatWConvertFP2I_RM_VL_V<riscv_vfcvt_rm_xu_f_vl, "PseudoVFWCVT_XU_F_V">;
defm : VPatWConvertFP2I_RM_VL_V<riscv_vfcvt_rm_x_f_vl, "PseudoVFWCVT_X_F_V">;

Expand Down Expand Up @@ -2694,8 +2629,6 @@ foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in {
}

// 13.19 Narrowing Floating-Point/Integer Type-Convert Instructions
defm : VPatNConvertFP2IVL_W_RM<riscv_vfcvt_xu_f_vl, "PseudoVFNCVT_XU_F_W">;
defm : VPatNConvertFP2IVL_W_RM<riscv_vfcvt_x_f_vl, "PseudoVFNCVT_X_F_W">;
defm : VPatNConvertFP2I_RM_VL_W<riscv_vfcvt_rm_xu_f_vl, "PseudoVFNCVT_XU_F_W">;
defm : VPatNConvertFP2I_RM_VL_W<riscv_vfcvt_rm_x_f_vl, "PseudoVFNCVT_X_F_W">;

Expand Down
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