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[AArch64] Disconnect FeatureUseScalarIncVL from FeatureSVE2. #114568

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[AArch64] Disconnect FeatureUseScalarIncVL from FeatureSVE2. #114568

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7 changes: 2 additions & 5 deletions llvm/lib/Target/AArch64/AArch64Features.td
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Original file line number Diff line number Diff line change
Expand Up @@ -358,12 +358,9 @@ def FeatureTHE : ExtensionWithMArch<"the", "THE", "FEAT_THE",
// Armv9.0 Architecture Extensions
//===----------------------------------------------------------------------===//

def FeatureUseScalarIncVL : SubtargetFeature<"use-scalar-inc-vl",
"UseScalarIncVL", "true", "Prefer inc/dec over add+cnt">;

def FeatureSVE2 : ExtensionWithMArch<"sve2", "SVE2", "FEAT_SVE2",
"Enable Scalable Vector Extension 2 (SVE2) instructions",
[FeatureSVE, FeatureUseScalarIncVL]>;
[FeatureSVE]>;

def FeatureSVE2AES : ExtensionWithMArch<"sve2-aes", "SVE2AES",
"FEAT_SVE_AES, FEAT_SVE_PMULL128",
Expand Down Expand Up @@ -403,7 +400,7 @@ def FeatureRME : Extension<"rme", "RME", "FEAT_RME",
"Enable Realm Management Extension">;

def FeatureSME : ExtensionWithMArch<"sme", "SME", "FEAT_SME",
"Enable Scalable Matrix Extension (SME)", [FeatureBF16, FeatureUseScalarIncVL]>;
"Enable Scalable Matrix Extension (SME)", [FeatureBF16]>;

def FeatureSMEF64F64 : ExtensionWithMArch<"sme-f64f64", "SMEF64F64", "FEAT_SME_F64F64",
"Enable Scalable Matrix Extension (SME) F64F64 instructions", [FeatureSME]>;
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12 changes: 12 additions & 0 deletions llvm/lib/Target/AArch64/AArch64Subtarget.cpp
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Expand Up @@ -93,6 +93,10 @@ static cl::opt<bool>
cl::init(false), cl::Hidden,
cl::desc("Enable subreg liveness tracking"));

static cl::opt<bool>
UseScalarIncVL("sve-use-scalar-inc-vl", cl::init(false), cl::Hidden,
cl::desc("Prefer add+cnt over addvl/inc/dec"));

unsigned AArch64Subtarget::getVectorInsertExtractBaseCost() const {
if (OverrideVectorInsertExtractBaseCost.getNumOccurrences() > 0)
return OverrideVectorInsertExtractBaseCost;
Expand Down Expand Up @@ -575,6 +579,14 @@ void AArch64Subtarget::mirFileLoaded(MachineFunction &MF) const {

bool AArch64Subtarget::useAA() const { return UseAA; }

bool AArch64Subtarget::useScalarIncVL() const {
// If SVE2 or SME is present (we are not SVE-1 only) and UseScalarIncVL
// is not otherwise set, enable it by default.
if (UseScalarIncVL.getNumOccurrences())
return UseScalarIncVL;
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@sdesmalen-arm sdesmalen-arm Nov 6, 2024

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I'd still recommend creating a separate variable for it in the Subtarget that gets initialised with the code you have here. That way a CPU could possibly override it in AArch64Subtarget::initializeProperties (if there is ever a need for that) and then the call to useScalarIncVL() can be inlined rather than ending up as a call. But this is just me nitpicking a bit :)

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@davemgreen davemgreen Nov 10, 2024

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Thanks - We would probably want go the other way and reintroduce the target features if we needed it for a specific CPU. The preferred way is for tuning features to control the options, which are applied to given cpus that they are relevant to.

return hasSVE2() || hasSME();
}

// If return address signing is enabled, tail calls are emitted as follows:
//
// ```
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2 changes: 2 additions & 0 deletions llvm/lib/Target/AArch64/AArch64Subtarget.h
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Expand Up @@ -417,6 +417,8 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
return DefaultSVETFOpts;
}

bool useScalarIncVL() const;
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@sdesmalen-arm sdesmalen-arm Nov 6, 2024

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nit: maybe add a comment to explain what useScalarIncVL means?


const char* getChkStkName() const {
if (isWindowsArm64EC())
return "#__chkstk_arm64ec";
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems-i32.ll
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@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s -check-prefix=NO_SCALAR_INC
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -mattr=+use-scalar-inc-vl < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -sve-use-scalar-inc-vl=true < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s

; INCB
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4 changes: 3 additions & 1 deletion llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll
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@@ -1,8 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -mattr=+use-scalar-inc-vl < %s | FileCheck %s -check-prefix=USE_SCALAR_INC
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -sve-use-scalar-inc-vl=true < %s | FileCheck %s -check-prefix=USE_SCALAR_INC
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s -check-prefix=USE_SCALAR_INC
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s -check-prefix=USE_SCALAR_INC
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 -sve-use-scalar-inc-vl=false < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -sve-use-scalar-inc-vl=false -force-streaming < %s | FileCheck %s

;
; CNTB
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3 changes: 2 additions & 1 deletion llvm/test/CodeGen/AArch64/sve-vl-arith.ll
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@@ -1,7 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -verify-machineinstrs < %s | FileCheck %s -check-prefix=NO_SCALAR_INC
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -mattr=+use-scalar-inc-vl -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -sve-use-scalar-inc-vl=true -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 -sve-use-scalar-inc-vl=false -verify-machineinstrs < %s | FileCheck %s -check-prefix=NO_SCALAR_INC

define <vscale x 8 x i16> @inch_vec(<vscale x 8 x i16> %a) {
; NO_SCALAR_INC-LABEL: inch_vec:
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