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[RISCV] Allow undef elements in isDeinterleaveShuffle #114585

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Merged
merged 3 commits into from
Nov 4, 2024
Merged

[RISCV] Allow undef elements in isDeinterleaveShuffle #114585

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946ac97
[RISCV] Allow undef elements in isDeinterleaveShuffle
preames Nov 1, 2024
b0ee8ad
Clang-format
preames Nov 1, 2024
1d4695f
Fix bug in prior version and add additional tests
preames Nov 4, 2024
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5 changes: 2 additions & 3 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4475,10 +4475,9 @@ static bool isDeinterleaveShuffle(MVT VT, MVT ContainerVT, SDValue V1,
if (Mask[0] != 0 && Mask[0] != 1)
return false;

// The others must increase by 2 each time.
// TODO: Support undef elements?
// The others must increase by 2 each time (or be undef).
for (unsigned i = 1; i != Mask.size(); ++i)
if (Mask[i] != Mask[i - 1] + 2)
if (Mask[i] != -1 && Mask[i] != Mask[0] + (int)i * 2)
return false;

return true;
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40 changes: 7 additions & 33 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
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Expand Up @@ -12,46 +12,20 @@ define {<3 x i32>, <3 x i32>} @load_factor2_v3(ptr %ptr) {
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; RV32-NEXT: vle32.v v10, (a0)
; RV32-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV32-NEXT: vslidedown.vi v9, v10, 2
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV32-NEXT: vwaddu.vv v8, v10, v9
; RV32-NEXT: li a0, -1
; RV32-NEXT: vwmaccu.vx v8, a0, v9
; RV32-NEXT: vmv.v.i v0, 4
; RV32-NEXT: vsetivli zero, 4, e32, m2, ta, ma
; RV32-NEXT: vslidedown.vi v12, v10, 4
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV32-NEXT: vrgather.vi v8, v12, 0, v0.t
; RV32-NEXT: vid.v v9
; RV32-NEXT: vadd.vv v9, v9, v9
; RV32-NEXT: vadd.vi v11, v9, 1
; RV32-NEXT: vrgather.vv v9, v10, v11
; RV32-NEXT: vrgather.vi v9, v12, 1, v0.t
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vnsrl.wi v8, v10, 0
; RV32-NEXT: li a0, 32
; RV32-NEXT: vnsrl.wx v9, v10, a0
; RV32-NEXT: ret
;
; RV64-LABEL: load_factor2_v3:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; RV64-NEXT: vle32.v v10, (a0)
; RV64-NEXT: li a0, 32
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vid.v v8
; RV64-NEXT: vadd.vv v8, v8, v8
; RV64-NEXT: vadd.vi v8, v8, 1
; RV64-NEXT: vrgather.vv v9, v10, v8
; RV64-NEXT: vmv.v.i v0, 4
; RV64-NEXT: vsetivli zero, 4, e32, m2, ta, ma
; RV64-NEXT: vslidedown.vi v12, v10, 4
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV64-NEXT: vrgather.vi v9, v12, 1, v0.t
; RV64-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v11, v10, 2
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64-NEXT: vwaddu.vv v8, v10, v11
; RV64-NEXT: li a0, -1
; RV64-NEXT: vwmaccu.vx v8, a0, v11
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; RV64-NEXT: vrgather.vi v8, v12, 0, v0.t
; RV64-NEXT: vnsrl.wx v9, v10, a0
; RV64-NEXT: vnsrl.wi v8, v10, 0
; RV64-NEXT: ret
%interleaved.vec = load <6 x i32>, ptr %ptr
%v0 = shufflevector <6 x i32> %interleaved.vec, <6 x i32> poison, <3 x i32> <i32 0, i32 2, i32 4>
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91 changes: 91 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
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Expand Up @@ -347,3 +347,94 @@ entry:
store <2 x double> %shuffle.i5, ptr %out, align 8
ret void
}

define void @vnsrl_0_i8_undef(ptr %in, ptr %out) {
; CHECK-LABEL: vnsrl_0_i8_undef:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 16, e8, mf2, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
entry:
%0 = load <16 x i8>, ptr %in, align 1
%shuffle.i5 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 undef, i32 undef>
store <8 x i8> %shuffle.i5, ptr %out, align 1
ret void
}

define void @vnsrl_0_i8_undef2(ptr %in, ptr %out) {
; CHECK-LABEL: vnsrl_0_i8_undef2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 16, e8, mf2, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
entry:
%0 = load <16 x i8>, ptr %in, align 1
%shuffle.i5 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12, i32 14>
store <8 x i8> %shuffle.i5, ptr %out, align 1
ret void
}

; TODO: Allow an undef initial element
define void @vnsrl_0_i8_undef3(ptr %in, ptr %out) {
; CHECK-LABEL: vnsrl_0_i8_undef3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 16, e8, mf2, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: lui a0, 24640
; CHECK-NEXT: addi a0, a0, 6
; CHECK-NEXT: vsetivli zero, 8, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT: vrgather.vv v10, v8, v9
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vadd.vv v9, v9, v9
; CHECK-NEXT: vadd.vi v9, v9, -8
; CHECK-NEXT: li a0, -32
; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 8
; CHECK-NEXT: vsetivli zero, 8, e8, mf4, ta, mu
; CHECK-NEXT: vrgather.vv v10, v8, v9, v0.t
; CHECK-NEXT: vse8.v v10, (a1)
; CHECK-NEXT: ret
entry:
%0 = load <16 x i8>, ptr %in, align 1
%shuffle.i5 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 undef, i32 undef, i32 4, i32 6, i32 6, i32 10, i32 12, i32 14>
store <8 x i8> %shuffle.i5, ptr %out, align 1
ret void
}

; Not a vnsrl (checking for a prior pattern matching bug)
define void @vnsrl_0_i8_undef_negative(ptr %in, ptr %out) {
; CHECK-LABEL: vnsrl_0_i8_undef_negative:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 16, e8, mf2, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: lui a0, %hi(.LCPI17_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI17_0)
; CHECK-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vrgather.vv v10, v8, v9
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vadd.vv v9, v9, v9
; CHECK-NEXT: vadd.vi v9, v9, -8
; CHECK-NEXT: li a0, 48
; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 8
; CHECK-NEXT: vsetivli zero, 8, e8, mf4, ta, mu
; CHECK-NEXT: vrgather.vv v10, v8, v9, v0.t
; CHECK-NEXT: vse8.v v10, (a1)
; CHECK-NEXT: ret
entry:
%0 = load <16 x i8>, ptr %in, align 1
%shuffle.i5 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 undef, i32 1>
store <8 x i8> %shuffle.i5, ptr %out, align 1
ret void
}
3 changes: 0 additions & 3 deletions llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
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Expand Up @@ -269,6 +269,3 @@ declare {<2 x float>, <2 x float>} @llvm.vector.deinterleave2.v4f32(<4 x float>)
declare {<8 x half>, <8 x half>} @llvm.vector.deinterleave2.v16f16(<16 x half>)
declare {<4 x float>, <4 x float>} @llvm.vector.deinterleave2.v8f32(<8 x float>)
declare {<2 x double>, <2 x double>} @llvm.vector.deinterleave2.v4f64(<4 x double>)
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; RV32: {{.*}}
; RV64: {{.*}}
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