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[AArch64] Define high bits of FPR and GPR registers (take 2) #114827

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Merged
merged 7 commits into from
Nov 14, 2024
Merged

[AArch64] Define high bits of FPR and GPR registers (take 2) #114827

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b325481
[AArch64] Define high bits of FPR and GPR registers.
sdesmalen-arm Oct 23, 2024
8dbcb52
Fixups
sdesmalen-arm Oct 30, 2024
dbcc23d
Add const to ReservedHi
sdesmalen-arm Nov 4, 2024
b4635da
Regenerate llvm-mca tests
sdesmalen-arm Nov 5, 2024
c96fbce
Document the _hi SubRegIndexes
sdesmalen-arm Nov 5, 2024
a82ac46
Fix llvm-mca not to consider artificial subregs
sdesmalen-arm Nov 8, 2024
ab05ae5
Clarify meaning of artificial
sdesmalen-arm Nov 12, 2024
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6 changes: 6 additions & 0 deletions llvm/include/llvm/MC/MCRegisterInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -129,6 +129,9 @@ struct MCRegisterDesc {

// Is true for constant registers.
bool IsConstant;

// Is true for artificial registers.
bool IsArtificial;
};

/// MCRegisterInfo base class - We assume that the target defines a static
Expand Down Expand Up @@ -396,6 +399,9 @@ class MCRegisterInfo {
/// Returns true if the given register is constant.
bool isConstant(MCRegister RegNo) const { return get(RegNo).IsConstant; }

/// Returns true if the given register is artificial.
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@davemgreen davemgreen Nov 11, 2024

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Is it worth explaining what Artificial means more precisely?

bool isArtificial(MCRegister RegNo) const { return get(RegNo).IsArtificial; }

/// Return the number of registers this target has (useful for
/// sizing arrays holding per register information)
unsigned getNumRegs() const {
Expand Down
14 changes: 11 additions & 3 deletions llvm/lib/MCA/HardwareUnits/RegisterFile.cpp
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Expand Up @@ -24,6 +24,11 @@ namespace mca {

const unsigned WriteRef::INVALID_IID = std::numeric_limits<unsigned>::max();

static std::function<bool(MCPhysReg)>
isNonArtificial(const MCRegisterInfo &MRI) {
return [&MRI](MCPhysReg R) { return !MRI.isArtificial(R); };
}

WriteRef::WriteRef(unsigned SourceIndex, WriteState *WS)
: IID(SourceIndex), WriteBackCycle(), WriteResID(), RegisterID(),
Write(WS) {}
Expand Down Expand Up @@ -282,7 +287,8 @@ void RegisterFile::addRegisterWrite(WriteRef Write,
MCPhysReg ZeroRegisterID =
WS.clearsSuperRegisters() ? RegID : WS.getRegisterID();
ZeroRegisters.setBitVal(ZeroRegisterID, IsWriteZero);
for (MCPhysReg I : MRI.subregs(ZeroRegisterID))
for (MCPhysReg I :
make_filter_range(MRI.subregs(ZeroRegisterID), isNonArtificial(MRI)))
ZeroRegisters.setBitVal(I, IsWriteZero);

// If this move has been eliminated, then method tryEliminateMoveOrSwap should
Expand All @@ -304,7 +310,8 @@ void RegisterFile::addRegisterWrite(WriteRef Write,
// Update the mapping for register RegID including its sub-registers.
RegisterMappings[RegID].first = Write;
RegisterMappings[RegID].second.AliasRegID = 0U;
for (MCPhysReg I : MRI.subregs(RegID)) {
for (MCPhysReg I :
make_filter_range(MRI.subregs(RegID), isNonArtificial(MRI))) {
RegisterMappings[I].first = Write;
RegisterMappings[I].second.AliasRegID = 0U;
}
Expand Down Expand Up @@ -472,7 +479,8 @@ bool RegisterFile::tryEliminateMoveOrSwap(MutableArrayRef<WriteState> Writes,
AliasedReg = RMAlias.AliasRegID;

RegisterMappings[AliasReg].second.AliasRegID = AliasedReg;
for (MCPhysReg I : MRI.subregs(AliasReg))
for (MCPhysReg I :
make_filter_range(MRI.subregs(AliasReg), isNonArtificial(MRI)))
RegisterMappings[I].second.AliasRegID = AliasedReg;

if (ZeroRegisters[RS.getRegisterID()]) {
Expand Down
5 changes: 4 additions & 1 deletion llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
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Expand Up @@ -1541,7 +1541,10 @@ static bool canRenameMOP(const MachineOperand &MOP,
// Note that this relies on the structure of the AArch64 register file. In
// particular, a subregister cannot be written without overwriting the
// whole register.
if (RegClass->HasDisjunctSubRegs) {
if (RegClass->HasDisjunctSubRegs && RegClass->CoveredBySubRegs &&
(TRI->getSubRegisterClass(RegClass, AArch64::dsub0) ||
TRI->getSubRegisterClass(RegClass, AArch64::qsub0) ||
TRI->getSubRegisterClass(RegClass, AArch64::zsub0))) {
LLVM_DEBUG(
dbgs()
<< " Cannot rename operands with multiple disjunct subregisters ("
Expand Down
58 changes: 56 additions & 2 deletions llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
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Expand Up @@ -424,6 +424,57 @@ AArch64RegisterInfo::explainReservedReg(const MachineFunction &MF,
return {};
}

static const MCPhysReg ReservedHi[] = {
AArch64::B0_HI, AArch64::B1_HI, AArch64::B2_HI, AArch64::B3_HI,
AArch64::B4_HI, AArch64::B5_HI, AArch64::B6_HI, AArch64::B7_HI,
AArch64::B8_HI, AArch64::B9_HI, AArch64::B10_HI, AArch64::B11_HI,
AArch64::B12_HI, AArch64::B13_HI, AArch64::B14_HI, AArch64::B15_HI,
AArch64::B16_HI, AArch64::B17_HI, AArch64::B18_HI, AArch64::B19_HI,
AArch64::B20_HI, AArch64::B21_HI, AArch64::B22_HI, AArch64::B23_HI,
AArch64::B24_HI, AArch64::B25_HI, AArch64::B26_HI, AArch64::B27_HI,
AArch64::B28_HI, AArch64::B29_HI, AArch64::B30_HI, AArch64::B31_HI,
AArch64::H0_HI, AArch64::H1_HI, AArch64::H2_HI, AArch64::H3_HI,
AArch64::H4_HI, AArch64::H5_HI, AArch64::H6_HI, AArch64::H7_HI,
AArch64::H8_HI, AArch64::H9_HI, AArch64::H10_HI, AArch64::H11_HI,
AArch64::H12_HI, AArch64::H13_HI, AArch64::H14_HI, AArch64::H15_HI,
AArch64::H16_HI, AArch64::H17_HI, AArch64::H18_HI, AArch64::H19_HI,
AArch64::H20_HI, AArch64::H21_HI, AArch64::H22_HI, AArch64::H23_HI,
AArch64::H24_HI, AArch64::H25_HI, AArch64::H26_HI, AArch64::H27_HI,
AArch64::H28_HI, AArch64::H29_HI, AArch64::H30_HI, AArch64::H31_HI,
AArch64::S0_HI, AArch64::S1_HI, AArch64::S2_HI, AArch64::S3_HI,
AArch64::S4_HI, AArch64::S5_HI, AArch64::S6_HI, AArch64::S7_HI,
AArch64::S8_HI, AArch64::S9_HI, AArch64::S10_HI, AArch64::S11_HI,
AArch64::S12_HI, AArch64::S13_HI, AArch64::S14_HI, AArch64::S15_HI,
AArch64::S16_HI, AArch64::S17_HI, AArch64::S18_HI, AArch64::S19_HI,
AArch64::S20_HI, AArch64::S21_HI, AArch64::S22_HI, AArch64::S23_HI,
AArch64::S24_HI, AArch64::S25_HI, AArch64::S26_HI, AArch64::S27_HI,
AArch64::S28_HI, AArch64::S29_HI, AArch64::S30_HI, AArch64::S31_HI,
AArch64::D0_HI, AArch64::D1_HI, AArch64::D2_HI, AArch64::D3_HI,
AArch64::D4_HI, AArch64::D5_HI, AArch64::D6_HI, AArch64::D7_HI,
AArch64::D8_HI, AArch64::D9_HI, AArch64::D10_HI, AArch64::D11_HI,
AArch64::D12_HI, AArch64::D13_HI, AArch64::D14_HI, AArch64::D15_HI,
AArch64::D16_HI, AArch64::D17_HI, AArch64::D18_HI, AArch64::D19_HI,
AArch64::D20_HI, AArch64::D21_HI, AArch64::D22_HI, AArch64::D23_HI,
AArch64::D24_HI, AArch64::D25_HI, AArch64::D26_HI, AArch64::D27_HI,
AArch64::D28_HI, AArch64::D29_HI, AArch64::D30_HI, AArch64::D31_HI,
AArch64::Q0_HI, AArch64::Q1_HI, AArch64::Q2_HI, AArch64::Q3_HI,
AArch64::Q4_HI, AArch64::Q5_HI, AArch64::Q6_HI, AArch64::Q7_HI,
AArch64::Q8_HI, AArch64::Q9_HI, AArch64::Q10_HI, AArch64::Q11_HI,
AArch64::Q12_HI, AArch64::Q13_HI, AArch64::Q14_HI, AArch64::Q15_HI,
AArch64::Q16_HI, AArch64::Q17_HI, AArch64::Q18_HI, AArch64::Q19_HI,
AArch64::Q20_HI, AArch64::Q21_HI, AArch64::Q22_HI, AArch64::Q23_HI,
AArch64::Q24_HI, AArch64::Q25_HI, AArch64::Q26_HI, AArch64::Q27_HI,
AArch64::Q28_HI, AArch64::Q29_HI, AArch64::Q30_HI, AArch64::Q31_HI,
AArch64::W0_HI, AArch64::W1_HI, AArch64::W2_HI, AArch64::W3_HI,
AArch64::W4_HI, AArch64::W5_HI, AArch64::W6_HI, AArch64::W7_HI,
AArch64::W8_HI, AArch64::W9_HI, AArch64::W10_HI, AArch64::W11_HI,
AArch64::W12_HI, AArch64::W13_HI, AArch64::W14_HI, AArch64::W15_HI,
AArch64::W16_HI, AArch64::W17_HI, AArch64::W18_HI, AArch64::W19_HI,
AArch64::W20_HI, AArch64::W21_HI, AArch64::W22_HI, AArch64::W23_HI,
AArch64::W24_HI, AArch64::W25_HI, AArch64::W26_HI, AArch64::W27_HI,
AArch64::W28_HI, AArch64::W29_HI, AArch64::W30_HI, AArch64::WSP_HI,
AArch64::WZR_HI};

BitVector
AArch64RegisterInfo::getStrictlyReservedRegs(const MachineFunction &MF) const {
const AArch64FrameLowering *TFI = getFrameLowering(MF);
Expand Down Expand Up @@ -490,7 +541,10 @@ AArch64RegisterInfo::getStrictlyReservedRegs(const MachineFunction &MF) const {
markSuperRegs(Reserved, AArch64::W28);
}

assert(checkAllSuperRegsMarked(Reserved));
for (Register R : ReservedHi)
Reserved.set(R);

assert(checkAllSuperRegsMarked(Reserved, ReservedHi));
return Reserved;
}

Expand All @@ -514,7 +568,7 @@ AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
markSuperRegs(Reserved, AArch64::LR);
}

assert(checkAllSuperRegsMarked(Reserved));
assert(checkAllSuperRegsMarked(Reserved, ReservedHi));
return Reserved;
}

Expand Down
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