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[RISCV] Lower fixed-length mgather/mscatter for zvfhmin/zvfbfmin #114945

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Merged
merged 3 commits into from
Nov 6, 2024
Merged

[RISCV] Lower fixed-length mgather/mscatter for zvfhmin/zvfbfmin #114945

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fde526c
Precommit tests
lukel97 Nov 5, 2024
86fa3e3
[RISCV] Lower mgather/mscatter for zvfhmin/zvfbfmin
lukel97 Nov 5, 2024
f726bb2
Update cost model tests and add some for fixed-length vectors
lukel97 Nov 5, 2024
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8 changes: 4 additions & 4 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1339,9 +1339,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::VECTOR_SHUFFLE, ISD::VECTOR_COMPRESS},
VT, Custom);

// FIXME: mload, mstore, mgather, mscatter, vp_gather/scatter can be
// FIXME: mload, mstore, vp_gather/scatter can be
// hoisted to here.
setOperationAction({ISD::LOAD, ISD::STORE}, VT, Custom);
setOperationAction({ISD::LOAD, ISD::STORE, ISD::MGATHER, ISD::MSCATTER},
VT, Custom);
setOperationAction({ISD::VP_LOAD, ISD::VP_STORE,
ISD::EXPERIMENTAL_VP_STRIDED_LOAD,
ISD::EXPERIMENTAL_VP_STRIDED_STORE},
Expand Down Expand Up @@ -1408,8 +1409,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction({ISD::BUILD_VECTOR, ISD::SCALAR_TO_VECTOR}, VT,
Custom);

setOperationAction(
{ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, VT, Custom);
setOperationAction({ISD::MLOAD, ISD::MSTORE}, VT, Custom);

setOperationAction({ISD::VP_GATHER, ISD::VP_SCATTER}, VT, Custom);

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7 changes: 6 additions & 1 deletion llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -270,7 +270,12 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
if (!ST->enableUnalignedVectorMem() && Alignment < ElemType.getStoreSize())
return false;

return TLI->isLegalElementTypeForRVV(ElemType);
// TODO: Move bf16/f16 support into isLegalElementTypeForRVV
return TLI->isLegalElementTypeForRVV(ElemType) ||
(DataTypeVT.getVectorElementType() == MVT::bf16 &&
ST->hasVInstructionsBF16Minimal()) ||
(DataTypeVT.getVectorElementType() == MVT::f16 &&
ST->hasVInstructionsF16Minimal());
}

bool isLegalMaskedGather(Type *DataType, Align Alignment) {
Expand Down
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