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[RISCV] Support Zfa in SiFive P600's scheduling model #115036

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[RISCV] Support Zfa in SiFive P600's scheduling model #115036

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10 changes: 9 additions & 1 deletion llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
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Original file line number Diff line number Diff line change
Expand Up @@ -283,6 +283,9 @@ def : WriteRes<WriteFCvtF64ToI32, [SiFiveP600F2I]>;
def : WriteRes<WriteFCvtF64ToI64, [SiFiveP600F2I]>;
def : WriteRes<WriteFCvtF64ToF16, [SiFiveP600FloatArith]>;
def : WriteRes<WriteFCvtF64ToF32, [SiFiveP600FloatArith]>;
def : WriteRes<WriteFRoundF16, [SiFiveP600FloatArith]>;
def : WriteRes<WriteFRoundF32, [SiFiveP600FloatArith]>;
def : WriteRes<WriteFRoundF64, [SiFiveP600FloatArith]>;

def : WriteRes<WriteFClass16, [SiFiveP600F2I]>;
def : WriteRes<WriteFClass32, [SiFiveP600F2I]>;
Expand All @@ -296,6 +299,9 @@ def : WriteRes<WriteFMovI32ToF32, [SiFiveP600MulI2F]>;
def : WriteRes<WriteFMovF32ToI32, [SiFiveP600F2I]>;
def : WriteRes<WriteFMovI64ToF64, [SiFiveP600MulI2F]>;
def : WriteRes<WriteFMovF64ToI64, [SiFiveP600F2I]>;
def : WriteRes<WriteFLI16, [SiFiveP600MulI2F]>;
def : WriteRes<WriteFLI32, [SiFiveP600MulI2F]>;
def : WriteRes<WriteFLI64, [SiFiveP600MulI2F]>;
}

// 6. Configuration-Setting Instructions
Expand Down Expand Up @@ -893,6 +899,9 @@ def : ReadAdvance<ReadFCvtF16ToF32, 0>;
def : ReadAdvance<ReadFCvtF32ToF16, 0>;
def : ReadAdvance<ReadFCvtF16ToF64, 0>;
def : ReadAdvance<ReadFCvtF64ToF16, 0>;
def : ReadAdvance<ReadFRoundF16, 0>;
def : ReadAdvance<ReadFRoundF32, 0>;
def : ReadAdvance<ReadFRoundF64, 0>;
def : ReadAdvance<ReadFMovF16ToI16, 0>;
def : ReadAdvance<ReadFMovI16ToF16, 0>;
def : ReadAdvance<ReadFMovF32ToI32, 0>;
Expand Down Expand Up @@ -1140,6 +1149,5 @@ defm : UnsupportedSchedZbc;
defm : UnsupportedSchedZbkb;
defm : UnsupportedSchedZbkx;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedZfa;
defm : UnsupportedSchedXsfvcp;
}
76 changes: 76 additions & 0 deletions llvm/test/tools/llvm-mca/RISCV/SiFiveP600/zfa.s
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@@ -0,0 +1,76 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -mattr=+zfa,+zfh -iterations=1 < %s | FileCheck %s

fli.h fa5, nan
fli.s fa5, nan
fli.d fa5, nan

fround.h fa0, fa0, rdn
froundnx.h fa0, fa0, rdn
fround.s fa0, fa0, rdn
froundnx.s fa0, fa0, rdn
fround.d fa0, fa0, rdn
froundnx.d fa0, fa0, rdn

# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 9
# CHECK-NEXT: Total Cycles: 15
# CHECK-NEXT: Total uOps: 9

# CHECK: Dispatch Width: 4
# CHECK-NEXT: uOps Per Cycle: 0.60
# CHECK-NEXT: IPC: 0.60
# CHECK-NEXT: Block RThroughput: 3.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 2 1.00 fli.h fa5, nan
# CHECK-NEXT: 1 2 1.00 fli.s fa5, nan
# CHECK-NEXT: 1 2 1.00 fli.d fa5, nan
# CHECK-NEXT: 1 2 0.50 fround.h fa0, fa0, rdn
# CHECK-NEXT: 1 2 0.50 froundnx.h fa0, fa0, rdn
# CHECK-NEXT: 1 2 0.50 fround.s fa0, fa0, rdn
# CHECK-NEXT: 1 2 0.50 froundnx.s fa0, fa0, rdn
# CHECK-NEXT: 1 2 0.50 fround.d fa0, fa0, rdn
# CHECK-NEXT: 1 2 0.50 froundnx.d fa0, fa0, rdn

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFiveP600Div
# CHECK-NEXT: [1] - SiFiveP600FEXQ0
# CHECK-NEXT: [2] - SiFiveP600FEXQ1
# CHECK-NEXT: [3] - SiFiveP600FloatDiv
# CHECK-NEXT: [4] - SiFiveP600IEXQ0
# CHECK-NEXT: [5] - SiFiveP600IEXQ1
# CHECK-NEXT: [6] - SiFiveP600IEXQ2
# CHECK-NEXT: [7] - SiFiveP600IEXQ3
# CHECK-NEXT: [8.0] - SiFiveP600LDST
# CHECK-NEXT: [8.1] - SiFiveP600LDST
# CHECK-NEXT: [9] - SiFiveP600VDiv
# CHECK-NEXT: [10] - SiFiveP600VEXQ0
# CHECK-NEXT: [11] - SiFiveP600VEXQ1
# CHECK-NEXT: [12] - SiFiveP600VFloatDiv
# CHECK-NEXT: [13] - SiFiveP600VLD
# CHECK-NEXT: [14] - SiFiveP600VST

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14]
# CHECK-NEXT: - 3.00 3.00 - - 3.00 - - - - - - - - - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions:
# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - fli.h fa5, nan
# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - fli.s fa5, nan
# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - fli.d fa5, nan
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - fround.h fa0, fa0, rdn
# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - froundnx.h fa0, fa0, rdn
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - fround.s fa0, fa0, rdn
# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - froundnx.s fa0, fa0, rdn
# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - fround.d fa0, fa0, rdn
# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - froundnx.d fa0, fa0, rdn
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