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[RISCV] Add test cases for RV64 i128<->half/float/double #115124

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merged 2 commits into from
Nov 6, 2024
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[RISCV] Add test cases for RV64 i128<->half/float/double #115124

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0c331c2
[RISCV] Add test cases for RV64 i128<->half/float/double
topperc Nov 6, 2024
329f601
fixup! Add common CHECK prefix.
topperc Nov 6, 2024
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95 changes: 95 additions & 0 deletions llvm/test/CodeGen/RISCV/rv64-double-convert-strict.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs -target-abi=lp64 \
; RUN: -disable-strictnode-mutation < %s | FileCheck %s -check-prefix=RV64ID
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs -target-abi=lp64d \
; RUN: -disable-strictnode-mutation < %s | FileCheck %s -check-prefix=RV64ID
; RUN: llc -mtriple=riscv64 -mattr=+zdinx -verify-machineinstrs -target-abi=lp64 \
; RUN: -disable-strictnode-mutation < %s | FileCheck %s -check-prefix=RV64IDINX

define i128 @fptosi_f64_to_i128(double %a) nounwind strictfp {
; RV64ID-LABEL: fptosi_f64_to_i128:
; RV64ID: # %bb.0:
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64ID-NEXT: call __fixdfti
; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64ID-NEXT: addi sp, sp, 16
; RV64ID-NEXT: ret
;
; RV64IDINX-LABEL: fptosi_f64_to_i128:
; RV64IDINX: # %bb.0:
; RV64IDINX-NEXT: addi sp, sp, -16
; RV64IDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IDINX-NEXT: call __fixdfti
; RV64IDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IDINX-NEXT: addi sp, sp, 16
; RV64IDINX-NEXT: ret
%1 = call i128 @llvm.experimental.constrained.fptosi.i128.f64(double %a, metadata !"fpexcept.strict")
ret i128 %1
}

define i128 @fptoui_f64_to_i128(double %a) nounwind strictfp {
; RV64ID-LABEL: fptoui_f64_to_i128:
; RV64ID: # %bb.0:
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64ID-NEXT: call __fixunsdfti
; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64ID-NEXT: addi sp, sp, 16
; RV64ID-NEXT: ret
;
; RV64IDINX-LABEL: fptoui_f64_to_i128:
; RV64IDINX: # %bb.0:
; RV64IDINX-NEXT: addi sp, sp, -16
; RV64IDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IDINX-NEXT: call __fixunsdfti
; RV64IDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IDINX-NEXT: addi sp, sp, 16
; RV64IDINX-NEXT: ret
%1 = call i128 @llvm.experimental.constrained.fptoui.i128.f64(double %a, metadata !"fpexcept.strict")
ret i128 %1
}

define double @sitofp_i128_to_f64(i128 %a) nounwind strictfp {
; RV64ID-LABEL: sitofp_i128_to_f64:
; RV64ID: # %bb.0:
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64ID-NEXT: call __floattidf
; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64ID-NEXT: addi sp, sp, 16
; RV64ID-NEXT: ret
;
; RV64IDINX-LABEL: sitofp_i128_to_f64:
; RV64IDINX: # %bb.0:
; RV64IDINX-NEXT: addi sp, sp, -16
; RV64IDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IDINX-NEXT: call __floattidf
; RV64IDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IDINX-NEXT: addi sp, sp, 16
; RV64IDINX-NEXT: ret
%1 = call double @llvm.experimental.constrained.sitofp.f64.i128(i128 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
ret double %1
}

define double @uitofp_i128_to_f64(i128 %a) nounwind strictfp {
; RV64ID-LABEL: uitofp_i128_to_f64:
; RV64ID: # %bb.0:
; RV64ID-NEXT: addi sp, sp, -16
; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64ID-NEXT: call __floatuntidf
; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64ID-NEXT: addi sp, sp, 16
; RV64ID-NEXT: ret
;
; RV64IDINX-LABEL: uitofp_i128_to_f64:
; RV64IDINX: # %bb.0:
; RV64IDINX-NEXT: addi sp, sp, -16
; RV64IDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IDINX-NEXT: call __floatuntidf
; RV64IDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IDINX-NEXT: addi sp, sp, 16
; RV64IDINX-NEXT: ret
%1 = call double @llvm.experimental.constrained.uitofp.f64.i128(i128 %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
ret double %1
}
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