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[AArch64] Add missing ASIMD FP convert instructions to scheduling model #115146

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Merged
merged 1 commit into from
Nov 6, 2024
Merged

[AArch64] Add missing ASIMD FP convert instructions to scheduling model #115146

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30 changes: 24 additions & 6 deletions llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1015,16 +1015,34 @@ def : InstRW<[V1Write_3c_1V02], (instregex "^FCVTNv[24]i32$",
"^FCVTXN(v[24]f32|v1i64)$")>;

// ASIMD FP convert, other, D-form F32 and Q-form F64
def : InstRW<[V1Write_3c_1V02], (instregex "^[FSU]CVT[AMNPZ][SU]v2f(32|64)$",
"^[SU]CVTFv2f(32|64)$")>;
def : InstRW<[V1Write_3c_1V02], (instregex "^FCVT[AMNPZ][SU]v2f(32|64)$",
"^FCVT[AMNPZ][SU]v2i(32|64)_shift$",
"^FCVT[AMNPZ][SU]v1i64$",
"^FCVTZ[SU]d$",
"^[SU]CVTFv2f(32|64)$",
"^[SU]CVTFv2i(32|64)_shift$",
"^[SU]CVTFv1i64$",
"^[SU]CVTFd$")>;

// ASIMD FP convert, other, D-form F16 and Q-form F32
def : InstRW<[V1Write_4c_2V02], (instregex "^[FSU]CVT[AMNPZ][SU]v4f(16|32)$",
"^[SU]CVTFv4f(16|32)$")>;
def : InstRW<[V1Write_4c_2V02], (instregex "^FCVT[AMNPZ][SU]v4f(16|32)$",
"^FCVT[AMNPZ][SU]v4i(16|32)_shift$",
"^FCVT[AMNPZ][SU]v1i32$",
"^FCVTZ[SU]s$",
"^[SU]CVTFv4f(16|32)$",
"^[SU]CVTFv4i(16|32)_shift$",
"^[SU]CVTFv1i32$",
"^[SU]CVTFs$")>;

// ASIMD FP convert, other, Q-form F16
def : InstRW<[V1Write_6c_4V02], (instregex "^[FSU]CVT[AMNPZ][SU]v8f16$",
"^[SU]CVTFv8f16$")>;
def : InstRW<[V1Write_6c_4V02], (instregex "^FCVT[AMNPZ][SU]v8f16$",
"^FCVT[AMNPZ][SU]v8i16_shift$",
"^FCVT[AMNPZ][SU]v1f16$",
"^FCVTZ[SU]h$",
"^[SU]CVTFv8f16$",
"^[SU]CVTFv8i16_shift$",
"^[SU]CVTFv1i16$",
"^[SU]CVTFh$")>;

// ASIMD FP divide, D-form, F16
// ASIMD FP square root, D-form, F16
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6 changes: 6 additions & 0 deletions llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1567,25 +1567,31 @@ def : InstRW<[V2Write_3c_1V02], (instregex "^FCVTN(v2|v4)i32",

// ASIMD FP convert, other, D-form F32 and Q-form F64
def : InstRW<[V2Write_3c_1V02], (instregex "^FCVT[AMNPZ][SU]v2f(32|64)$",
"^FCVT[AMNPZ][SU]v2i(32|64)_shift$",
"^FCVT[AMNPZ][SU]v1i64$",
"^FCVTZ[SU]d$",
"^[SU]CVTFv2f(32|64)$",
"^[SU]CVTFv2i(32|64)_shift$",
"^[SU]CVTFv1i64$",
"^[SU]CVTFd$")>;

// ASIMD FP convert, other, D-form F16 and Q-form F32
def : InstRW<[V2Write_4c_2V02], (instregex "^FCVT[AMNPZ][SU]v4f(16|32)$",
"^FCVT[AMNPZ][SU]v4i(16|32)_shift$",
"^FCVT[AMNPZ][SU]v1i32$",
"^FCVTZ[SU]s$",
"^[SU]CVTFv4f(16|32)$",
"^[SU]CVTFv4i(16|32)_shift$",
"^[SU]CVTFv1i32$",
"^[SU]CVTFs$")>;

// ASIMD FP convert, other, Q-form F16
def : InstRW<[V2Write_6c_4V02], (instregex "^FCVT[AMNPZ][SU]v8f16$",
"^FCVT[AMNPZ][SU]v8i16_shift$",
"^FCVT[AMNPZ][SU]v1f16$",
"^FCVTZ[SU]h$",
"^[SU]CVTFv8f16$",
"^[SU]CVTFv8i16_shift$",
"^[SU]CVTFv1i16$",
"^[SU]CVTFh$")>;

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