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[LLVM][ARM] Latency mutations for cortex m55,m7 and m85 #115153

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Nov 13, 2024
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[LLVM][ARM] Latency mutations for cortex m55,m7 and m85 #115153

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[LLVM][ARM] Latency mutations for cortex m55,m7 and m85
dpenry Nov 4, 2024
8893ff1
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nasherm Nov 7, 2024
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28 changes: 28 additions & 0 deletions llvm/lib/Target/ARM/ARMBaseInstrInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -973,6 +973,34 @@ unsigned getBLXOpcode(const MachineFunction &MF);
unsigned gettBLXrOpcode(const MachineFunction &MF);
unsigned getBLXpredOpcode(const MachineFunction &MF);

inline bool isMVEVectorInstruction(const MachineInstr *MI) {
// This attempts to remove non-mve instructions (scalar shifts), which
// are just DPU CX instruction.
switch (MI->getOpcode()) {
case ARM::MVE_SQSHL:
case ARM::MVE_SRSHR:
case ARM::MVE_UQSHL:
case ARM::MVE_URSHR:
case ARM::MVE_SQRSHR:
case ARM::MVE_UQRSHL:
case ARM::MVE_ASRLr:
case ARM::MVE_ASRLi:
case ARM::MVE_LSLLr:
case ARM::MVE_LSLLi:
case ARM::MVE_LSRL:
case ARM::MVE_SQRSHRL:
case ARM::MVE_SQSHLL:
case ARM::MVE_SRSHRL:
case ARM::MVE_UQRSHLL:
case ARM::MVE_UQSHLL:
case ARM::MVE_URSHRL:
return false;
}
const MCInstrDesc &MCID = MI->getDesc();
uint64_t Flags = MCID.TSFlags;
return (Flags & ARMII::DomainMask) == ARMII::DomainMVE;
}

} // end namespace llvm

#endif // LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
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