[NVPTX] Set cache line size to 128 for __GCC_DESTRUCTIVE_SIZE

[jhuber6]

Summary:
According to the white papers, the cache line size on NVPTX
architectures is 128 bytes. This should be what's returned by these
preprocessor macros.

[llvmbot]

@llvm/pr-subscribers-clang

Author: Joseph Huber (jhuber6)

Changes

Summary:
According to the white papers, the cache line size on NVPTX
architectures is 128 bytes. This should be what's returned by these
preprocessor macros.

---

Full diff: https://github.com/llvm/llvm-project/pull/115248.diff

1 Files Affected:

• (modified) clang/lib/Basic/Targets/NVPTX.h (+4)

diff --git a/clang/lib/Basic/Targets/NVPTX.h b/clang/lib/Basic/Targets/NVPTX.h
index 165b28a60fb2a9..b1a07cdc6ed6bc 100644
--- a/clang/lib/Basic/Targets/NVPTX.h
+++ b/clang/lib/Basic/Targets/NVPTX.h
@@ -186,6 +186,10 @@ class LLVM_LIBRARY_VISIBILITY NVPTXTargetInfo : public TargetInfo {
   bool hasBFloat16Type() const override { return true; }
 
   OffloadArch getGPU() const { return GPU; }
+
+  std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override {
+    return std::make_pair(128, 128);
+  }
 };
 } // namespace targets
 } // namespace clang

[jhuber6]

ping

[cor3ntin]

We probably want some test for this change

[jhuber6]

There's also the question of when done from CUDA, perhaps we should make this match the aux triple if present.

[Artem-B]

I'm not sure the host-side concepts of false sharing even applies to the GPU.
For starters, L1 and L2 caches are not necessarily coherent. Also, L1 cache provides very little temporal locality and is mostly used for coalescing smaller transactions from multiple threads in a warp, so the concept of false sharing is moot -- threads rarely get to touch the same cache line, again.

As such, I do not think the changes makes any difference in terms of performance of the generated code.

However, there's an argument to be made that the host does care about __GCC_DESTRUCTIVE_SIZE, and if NVPTX back-end overrides it for the GPU compilations, it may result in observable differences between host and device compilations. That's something we want to minimize.

So, unless there's a specific reason we need to set the values differently from the host, I'd prefer to keep them matching.

Right now it appears that neither NVPTX nor X86 override this parameter, so we happen to be in sync.
Considering that for a GPU it's likely a "don't care" parameter, I think we should derive it from the host, similarly to other properties.