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[RISCV] Skip DAG combine for bitcast fabs/fneg #115325

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Merged
merged 1 commit into from
Nov 8, 2024
Merged

[RISCV] Skip DAG combine for bitcast fabs/fneg #115325

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2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -17075,7 +17075,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
// fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
// fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) ||
!Op0.getNode()->hasOneUse())
!Op0.getNode()->hasOneUse() || Subtarget.hasStdExtZdinx())
break;
SDValue NewSplitF64 =
DAG.getNode(RISCVISD::SplitF64, DL, DAG.getVTList(MVT::i32, MVT::i32),
Expand Down
7 changes: 2 additions & 5 deletions llvm/test/CodeGen/RISCV/double-arith.ll
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Expand Up @@ -844,8 +844,7 @@ define double @fnmadd_d_3(double %a, double %b, double %c) nounwind {
; RV32IZFINXZDINX-LABEL: fnmadd_d_3:
; RV32IZFINXZDINX: # %bb.0:
; RV32IZFINXZDINX-NEXT: fmadd.d a0, a0, a2, a4
; RV32IZFINXZDINX-NEXT: lui a2, 524288
; RV32IZFINXZDINX-NEXT: xor a1, a1, a2
; RV32IZFINXZDINX-NEXT: fneg.d a0, a0
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fnmadd_d_3:
Expand Down Expand Up @@ -890,9 +889,7 @@ define double @fnmadd_nsz(double %a, double %b, double %c) nounwind {
;
; RV32IZFINXZDINX-LABEL: fnmadd_nsz:
; RV32IZFINXZDINX: # %bb.0:
; RV32IZFINXZDINX-NEXT: fmadd.d a0, a0, a2, a4
; RV32IZFINXZDINX-NEXT: lui a2, 524288
; RV32IZFINXZDINX-NEXT: xor a1, a1, a2
; RV32IZFINXZDINX-NEXT: fnmadd.d a0, a0, a2, a4
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fnmadd_nsz:
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6 changes: 2 additions & 4 deletions llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
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Expand Up @@ -36,8 +36,7 @@ define double @fneg(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fneg:
; RV32IZFINXZDINX: # %bb.0:
; RV32IZFINXZDINX-NEXT: lui a2, 524288
; RV32IZFINXZDINX-NEXT: xor a1, a1, a2
; RV32IZFINXZDINX-NEXT: fneg.d a0, a0
; RV32IZFINXZDINX-NEXT: ret
;
; RV64I-LABEL: fneg:
Expand Down Expand Up @@ -79,8 +78,7 @@ define double @fabs(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fabs:
; RV32IZFINXZDINX: # %bb.0:
; RV32IZFINXZDINX-NEXT: slli a1, a1, 1
; RV32IZFINXZDINX-NEXT: srli a1, a1, 1
; RV32IZFINXZDINX-NEXT: fabs.d a0, a0
; RV32IZFINXZDINX-NEXT: ret
;
; RV64I-LABEL: fabs:
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3 changes: 1 addition & 2 deletions llvm/test/CodeGen/RISCV/double-intrinsics.ll
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Expand Up @@ -678,8 +678,7 @@ define double @fabs_f64(double %a) nounwind {
;
; RV32IZFINXZDINX-LABEL: fabs_f64:
; RV32IZFINXZDINX: # %bb.0:
; RV32IZFINXZDINX-NEXT: slli a1, a1, 1
; RV32IZFINXZDINX-NEXT: srli a1, a1, 1
; RV32IZFINXZDINX-NEXT: fabs.d a0, a0
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: fabs_f64:
Expand Down
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