-
Notifications
You must be signed in to change notification settings - Fork 15.3k
[AMDGPU][True16][MC] update true16 flag on vinterp test #115356
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Merged
broxigarchen
merged 1 commit into
llvm:main
from
broxigarchen:main-merge-true16-vinterp-mc-copytest
Nov 7, 2024
Merged
Changes from all commits
Commits
File filter
Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
There are no files selected for viewing
173 changes: 88 additions & 85 deletions
173
...MC/Disassembler/AMDGPU/vinterp-fake16.txt → llvm/test/MC/Disassembler/AMDGPU/vinterp.txt
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,252 +1,255 @@ | ||
| # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -disassemble %s | FileCheck -strict-whitespace -check-prefix=CHECK %s | ||
| # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -disassemble %s | FileCheck -strict-whitespace -check-prefix=CHECK %s | ||
| # NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 | ||
| # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -disassemble %s | FileCheck -strict-whitespace -check-prefixes=CHECK %s | ||
| # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -disassemble %s | FileCheck -strict-whitespace -check-prefixes=CHECK %s | ||
| # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -disassemble %s | FileCheck -strict-whitespace -check-prefixes=CHECK %s | ||
| # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -disassemble %s | FileCheck -strict-whitespace -check-prefixes=CHECK %s | ||
|
|
||
| # CHECK: v_interp_p10_f32 v0, v1, v2, v3 wait_exp:0{{$}} | ||
| 0x00,0x00,0x00,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p10_f32 v0, v1, v2, v3 wait_exp:0 | ||
|
|
||
| # Check that unused bits in the encoding are ignored. | ||
| # CHECK: v_interp_p10_f32 v0, v1, v2, v3 wait_exp:0{{$}} | ||
| 0x00,0x00,0x80,0xcd,0x01,0x05,0x0e,0x1c | ||
| # CHECK: v_interp_p10_f32 v0, v1, v2, v3 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p10_f32 v1, v10, v20, v30 wait_exp:0{{$}} | ||
| 0x01,0x00,0x00,0xcd,0x0a,0x29,0x7a,0x04 | ||
| # CHECK: v_interp_p10_f32 v1, v10, v20, v30 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p10_f32 v2, v11, v21, v31 wait_exp:0{{$}} | ||
| 0x02,0x00,0x00,0xcd,0x0b,0x2b,0x7e,0x04 | ||
| # CHECK: v_interp_p10_f32 v2, v11, v21, v31 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p10_f32 v3, v12, v22, v32 wait_exp:0{{$}} | ||
| 0x03,0x00,0x00,0xcd,0x0c,0x2d,0x82,0x04 | ||
| # CHECK: v_interp_p10_f32 v3, v12, v22, v32 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p10_f32 v0, v1, v2, v3 clamp wait_exp:0{{$}} | ||
| 0x00,0x80,0x00,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p10_f32 v0, v1, v2, v3 clamp wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p10_f32 v0, -v1, v2, v3 wait_exp:0{{$}} | ||
| 0x00,0x00,0x00,0xcd,0x01,0x05,0x0e,0x24 | ||
| # CHECK: v_interp_p10_f32 v0, -v1, v2, v3 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p10_f32 v0, v1, -v2, v3 wait_exp:0{{$}} | ||
| 0x00,0x00,0x00,0xcd,0x01,0x05,0x0e,0x44 | ||
| # CHECK: v_interp_p10_f32 v0, v1, -v2, v3 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p10_f32 v0, v1, v2, -v3 wait_exp:0{{$}} | ||
| 0x00,0x00,0x00,0xcd,0x01,0x05,0x0e,0x84 | ||
| # CHECK: v_interp_p10_f32 v0, v1, v2, -v3 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p10_f32 v0, v1, v2, v3 wait_exp:1{{$}} | ||
| 0x00,0x01,0x00,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p10_f32 v0, v1, v2, v3 wait_exp:1 | ||
|
|
||
| # CHECK: v_interp_p10_f32 v0, v1, v2, v3 wait_exp:7{{$}} | ||
| 0x00,0x07,0x00,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p10_f32 v0, v1, v2, v3 wait_exp:7 | ||
|
|
||
| # CHECK: v_interp_p10_f32 v0, v1, v2, v3 clamp wait_exp:7{{$}} | ||
| 0x00,0x87,0x00,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p10_f32 v0, v1, v2, v3 clamp wait_exp:7 | ||
|
|
||
| # CHECK: v_interp_p2_f32 v0, v1, v2, v3 wait_exp:0{{$}} | ||
| 0x00,0x00,0x01,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p2_f32 v0, v1, v2, v3 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p2_f32 v1, v10, v20, v30 wait_exp:0{{$}} | ||
| 0x01,0x00,0x01,0xcd,0x0a,0x29,0x7a,0x04 | ||
| # CHECK: v_interp_p2_f32 v1, v10, v20, v30 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p2_f32 v2, v11, v21, v31 wait_exp:0{{$}} | ||
| 0x02,0x00,0x01,0xcd,0x0b,0x2b,0x7e,0x04 | ||
| # CHECK: v_interp_p2_f32 v2, v11, v21, v31 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p2_f32 v3, v12, v22, v32 wait_exp:0{{$}} | ||
| 0x03,0x00,0x01,0xcd,0x0c,0x2d,0x82,0x04 | ||
| # CHECK: v_interp_p2_f32 v3, v12, v22, v32 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p2_f32 v0, v1, v2, v3 clamp wait_exp:0{{$}} | ||
| 0x00,0x80,0x01,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p2_f32 v0, v1, v2, v3 clamp wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p2_f32 v0, -v1, v2, v3 wait_exp:0{{$}} | ||
| 0x00,0x00,0x01,0xcd,0x01,0x05,0x0e,0x24 | ||
| # CHECK: v_interp_p2_f32 v0, -v1, v2, v3 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p2_f32 v0, v1, -v2, v3 wait_exp:0{{$}} | ||
| 0x00,0x00,0x01,0xcd,0x01,0x05,0x0e,0x44 | ||
| # CHECK: v_interp_p2_f32 v0, v1, -v2, v3 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p2_f32 v0, v1, v2, -v3 wait_exp:0{{$}} | ||
| 0x00,0x00,0x01,0xcd,0x01,0x05,0x0e,0x84 | ||
| # CHECK: v_interp_p2_f32 v0, v1, v2, -v3 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p2_f32 v0, v1, v2, v3 wait_exp:1{{$}} | ||
| 0x00,0x01,0x01,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p2_f32 v0, v1, v2, v3 wait_exp:1 | ||
|
|
||
| # CHECK: v_interp_p2_f32 v0, v1, v2, v3 wait_exp:7{{$}} | ||
| 0x00,0x07,0x01,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p2_f32 v0, v1, v2, v3 wait_exp:7 | ||
|
|
||
| # CHECK: v_interp_p2_f32 v0, v1, v2, v3 clamp wait_exp:7{{$}} | ||
| 0x00,0x87,0x01,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p2_f32 v0, v1, v2, v3 clamp wait_exp:7 | ||
|
|
||
| # CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 wait_exp:0{{$}} | ||
| 0x00,0x00,0x02,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p10_f16_f32 v0, -v1, v2, v3 wait_exp:0{{$}} | ||
| 0x00,0x00,0x02,0xcd,0x01,0x05,0x0e,0x24 | ||
| # CHECK: v_interp_p10_f16_f32 v0, -v1, v2, v3 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p10_f16_f32 v0, v1, -v2, v3 wait_exp:0{{$}} | ||
| 0x00,0x00,0x02,0xcd,0x01,0x05,0x0e,0x44 | ||
| # CHECK: v_interp_p10_f16_f32 v0, v1, -v2, v3 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p10_f16_f32 v0, v1, v2, -v3 wait_exp:0{{$}} | ||
| 0x00,0x00,0x02,0xcd,0x01,0x05,0x0e,0x84 | ||
| # CHECK: v_interp_p10_f16_f32 v0, v1, v2, -v3 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 clamp wait_exp:0{{$}} | ||
| 0x00,0x80,0x02,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 clamp wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 wait_exp:1{{$}} | ||
| 0x00,0x01,0x02,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 wait_exp:1 | ||
|
|
||
| # CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 wait_exp:7{{$}} | ||
| 0x00,0x07,0x02,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 wait_exp:7 | ||
|
|
||
| # CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,0] wait_exp:0{{$}} | ||
| 0x00,0x08,0x02,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,0] wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[0,1,0,0] wait_exp:0{{$}} | ||
| 0x00,0x10,0x02,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[0,1,0,0] wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[0,0,1,0] wait_exp:0{{$}} | ||
| 0x00,0x20,0x02,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[0,0,1,0] wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[0,0,0,1] wait_exp:0{{$}} | ||
| 0x00,0x40,0x02,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[0,0,0,1] wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[1,1,1,1] wait_exp:0{{$}} | ||
| 0x00,0x78,0x02,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[1,1,1,1] wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,1] wait_exp:5{{$}} | ||
| 0x00,0x4d,0x02,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,1] wait_exp:5 | ||
|
|
||
| # CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 clamp op_sel:[1,0,0,1] wait_exp:5{{$}} | ||
| 0x00,0xcd,0x02,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p10_f16_f32 v0, v1, v2, v3 clamp op_sel:[1,0,0,1] wait_exp:5 | ||
|
|
||
| # CHECK: v_interp_p10_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5{{$}} | ||
| 0x00,0xcd,0x02,0xcd,0x01,0x05,0x0e,0xe4 | ||
| # CHECK: v_interp_p10_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5 | ||
|
|
||
| # CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 wait_exp:0{{$}} | ||
| 0x00,0x00,0x03,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p2_f16_f32 v0, -v1, v2, v3 wait_exp:0{{$}} | ||
| 0x00,0x00,0x03,0xcd,0x01,0x05,0x0e,0x24 | ||
| # CHECK: v_interp_p2_f16_f32 v0, -v1, v2, v3 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p2_f16_f32 v0, v1, -v2, v3 wait_exp:0{{$}} | ||
| 0x00,0x00,0x03,0xcd,0x01,0x05,0x0e,0x44 | ||
| # CHECK: v_interp_p2_f16_f32 v0, v1, -v2, v3 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p2_f16_f32 v0, v1, v2, -v3 wait_exp:0{{$}} | ||
| 0x00,0x00,0x03,0xcd,0x01,0x05,0x0e,0x84 | ||
| # CHECK: v_interp_p2_f16_f32 v0, v1, v2, -v3 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 clamp wait_exp:0{{$}} | ||
| 0x00,0x80,0x03,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 clamp wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 wait_exp:1{{$}} | ||
| 0x00,0x01,0x03,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 wait_exp:1 | ||
|
|
||
| # CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 wait_exp:7{{$}} | ||
| 0x00,0x07,0x03,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 wait_exp:7 | ||
|
|
||
| # CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,0] wait_exp:0{{$}} | ||
| 0x00,0x08,0x03,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,0] wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[0,1,0,0] wait_exp:0{{$}} | ||
| 0x00,0x10,0x03,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[0,1,0,0] wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[0,0,1,0] wait_exp:0{{$}} | ||
| 0x00,0x20,0x03,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[0,0,1,0] wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[0,0,0,1] wait_exp:0{{$}} | ||
| 0x00,0x40,0x03,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[0,0,0,1] wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[1,1,1,1] wait_exp:0{{$}} | ||
| 0x00,0x78,0x03,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[1,1,1,1] wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,1] wait_exp:5{{$}} | ||
| 0x00,0x4d,0x03,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,1] wait_exp:5 | ||
|
|
||
| # CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 clamp op_sel:[1,0,0,1] wait_exp:5{{$}} | ||
| 0x00,0xcd,0x03,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p2_f16_f32 v0, v1, v2, v3 clamp op_sel:[1,0,0,1] wait_exp:5 | ||
|
|
||
| # CHECK: v_interp_p2_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5{{$}} | ||
| 0x00,0xcd,0x03,0xcd,0x01,0x05,0x0e,0xe4 | ||
| # CHECK: v_interp_p2_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5 | ||
|
|
||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 wait_exp:0{{$}} | ||
| 0x00,0x00,0x04,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, -v1, v2, v3 wait_exp:0{{$}} | ||
| 0x00,0x00,0x04,0xcd,0x01,0x05,0x0e,0x24 | ||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, -v1, v2, v3 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, v1, -v2, v3 wait_exp:0{{$}} | ||
| 0x00,0x00,0x04,0xcd,0x01,0x05,0x0e,0x44 | ||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, v1, -v2, v3 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, -v3 wait_exp:0{{$}} | ||
| 0x00,0x00,0x04,0xcd,0x01,0x05,0x0e,0x84 | ||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, -v3 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 clamp wait_exp:0{{$}} | ||
| 0x00,0x80,0x04,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 clamp wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 wait_exp:1{{$}} | ||
| 0x00,0x01,0x04,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 wait_exp:1 | ||
|
|
||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 wait_exp:7{{$}} | ||
| 0x00,0x07,0x04,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 wait_exp:7 | ||
|
|
||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,0] wait_exp:0{{$}} | ||
| 0x00,0x08,0x04,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,0] wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,1,0,0] wait_exp:0{{$}} | ||
| 0x00,0x10,0x04,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,1,0,0] wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,0,1,0] wait_exp:0{{$}} | ||
| 0x00,0x20,0x04,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,0,1,0] wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,0,0,1] wait_exp:0{{$}} | ||
| 0x00,0x40,0x04,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,0,0,1] wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,1,1,1] wait_exp:0{{$}} | ||
| 0x00,0x78,0x04,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,1,1,1] wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,1] wait_exp:5{{$}} | ||
| 0x00,0x4d,0x04,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,1] wait_exp:5 | ||
|
|
||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 clamp op_sel:[1,0,0,1] wait_exp:5{{$}} | ||
| 0x00,0xcd,0x04,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 clamp op_sel:[1,0,0,1] wait_exp:5 | ||
|
|
||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5{{$}} | ||
| 0x00,0xcd,0x04,0xcd,0x01,0x05,0x0e,0xe4 | ||
| # CHECK: v_interp_p10_rtz_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5 | ||
|
|
||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 wait_exp:0{{$}} | ||
| 0x00,0x00,0x05,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, -v1, v2, v3 wait_exp:0{{$}} | ||
| 0x00,0x00,0x05,0xcd,0x01,0x05,0x0e,0x24 | ||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, -v1, v2, v3 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, v1, -v2, v3 wait_exp:0{{$}} | ||
| 0x00,0x00,0x05,0xcd,0x01,0x05,0x0e,0x44 | ||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, v1, -v2, v3 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, -v3 wait_exp:0{{$}} | ||
| 0x00,0x00,0x05,0xcd,0x01,0x05,0x0e,0x84 | ||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, -v3 wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 clamp wait_exp:0{{$}} | ||
| 0x00,0x80,0x05,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 clamp wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 wait_exp:1{{$}} | ||
| 0x00,0x01,0x05,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 wait_exp:1 | ||
|
|
||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 wait_exp:7{{$}} | ||
| 0x00,0x07,0x05,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 wait_exp:7 | ||
|
|
||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,0] wait_exp:0{{$}} | ||
| 0x00,0x08,0x05,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,0] wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,1,0,0] wait_exp:0{{$}} | ||
| 0x00,0x10,0x05,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,1,0,0] wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,0,1,0] wait_exp:0{{$}} | ||
| 0x00,0x20,0x05,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,0,1,0] wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,0,0,1] wait_exp:0{{$}} | ||
| 0x00,0x40,0x05,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,0,0,1] wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,1,1,1] wait_exp:0{{$}} | ||
| 0x00,0x78,0x05,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,1,1,1] wait_exp:0 | ||
|
|
||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,1] wait_exp:5{{$}} | ||
| 0x00,0x4d,0x05,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,1] wait_exp:5 | ||
|
|
||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 clamp op_sel:[1,0,0,1] wait_exp:5{{$}} | ||
| 0x00,0xcd,0x05,0xcd,0x01,0x05,0x0e,0x04 | ||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 clamp op_sel:[1,0,0,1] wait_exp:5 | ||
|
|
||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5{{$}} | ||
| 0x00,0xcd,0x05,0xcd,0x01,0x05,0x0e,0xe4 | ||
| # CHECK: v_interp_p2_rtz_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5 | ||
Oops, something went wrong.
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
@broxigarchen Why don't these tests do
-show-encoding? We do seem to have encodings checked downstream.