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[RISCV][GISel] Add G_ZEXT to RISCVInstructionSelector::selectZExtBits. #115391

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Merged
merged 1 commit into from
Nov 8, 2024
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[RISCV][GISel] Add G_ZEXT to RISCVInstructionSelector::selectZExtBits. #115391

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4 changes: 4 additions & 0 deletions llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -288,6 +288,10 @@ RISCVInstructionSelector::selectZExtBits(MachineOperand &Root,
return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(RegX); }}};
}

if (mi_match(RootReg, *MRI, m_GZExt(m_Reg(RegX))) &&
MRI->getType(RegX).getScalarSizeInBits() == Bits)
return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(RegX); }}};

unsigned Size = MRI->getType(RootReg).getScalarSizeInBits();
if (KB->maskedValueIsZero(RootReg, APInt::getBitsSetFrom(Size, Bits)))
return {{[=](MachineInstrBuilder &MIB) { MIB.add(Root); }}};
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4 changes: 1 addition & 3 deletions llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
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Expand Up @@ -300,9 +300,7 @@ define signext i32 @fcvt_d_wu_demanded_bits(i32 signext %0, ptr %1) nounwind {
; RV64IFD-LABEL: fcvt_d_wu_demanded_bits:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addiw a0, a0, 1
; RV64IFD-NEXT: slli a2, a0, 32
; RV64IFD-NEXT: srli a2, a2, 32
; RV64IFD-NEXT: fcvt.d.wu fa5, a2
; RV64IFD-NEXT: fcvt.d.wu fa5, a0
; RV64IFD-NEXT: fsd fa5, 0(a1)
; RV64IFD-NEXT: ret
%3 = add i32 %0, 1
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4 changes: 1 addition & 3 deletions llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
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Expand Up @@ -272,9 +272,7 @@ define signext i32 @fcvt_s_wu_demanded_bits(i32 signext %0, ptr %1) nounwind {
; RV64IF-LABEL: fcvt_s_wu_demanded_bits:
; RV64IF: # %bb.0:
; RV64IF-NEXT: addiw a0, a0, 1
; RV64IF-NEXT: slli a2, a0, 32
; RV64IF-NEXT: srli a2, a2, 32
; RV64IF-NEXT: fcvt.s.wu fa5, a2
; RV64IF-NEXT: fcvt.s.wu fa5, a0
; RV64IF-NEXT: fsw fa5, 0(a1)
; RV64IF-NEXT: ret
%3 = add i32 %0, 1
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