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[Target] Migrate away from PointerUnion::{is,get,dyn_cast} (NFC) #115623

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Merged
merged 1 commit into from
Nov 10, 2024
Merged

[Target] Migrate away from PointerUnion::{is,get,dyn_cast} (NFC) #115623

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12 changes: 6 additions & 6 deletions llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -995,9 +995,9 @@ static bool selectDebugInstr(MachineInstr &I, MachineRegisterInfo &MRI,
LLT Ty = MRI.getType(Reg);
const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
const TargetRegisterClass *RC =
RegClassOrBank.dyn_cast<const TargetRegisterClass *>();
dyn_cast<const TargetRegisterClass *>(RegClassOrBank);
if (!RC) {
const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>();
const RegisterBank &RB = *cast<const RegisterBank *>(RegClassOrBank);
RC = getRegClassForTypeOnBank(Ty, RB);
if (!RC) {
LLVM_DEBUG(
Expand Down Expand Up @@ -2590,14 +2590,14 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
const RegClassOrRegBank &RegClassOrBank =
MRI.getRegClassOrRegBank(DefReg);

const TargetRegisterClass *DefRC
= RegClassOrBank.dyn_cast<const TargetRegisterClass *>();
const TargetRegisterClass *DefRC =
dyn_cast<const TargetRegisterClass *>(RegClassOrBank);
if (!DefRC) {
if (!DefTy.isValid()) {
LLVM_DEBUG(dbgs() << "PHI operand has no type, not a gvreg?\n");
return false;
}
const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>();
const RegisterBank &RB = *cast<const RegisterBank *>(RegClassOrBank);
DefRC = getRegClassForTypeOnBank(DefTy, RB);
if (!DefRC) {
LLVM_DEBUG(dbgs() << "PHI operand has unexpected size/bank\n");
Expand Down Expand Up @@ -4677,7 +4677,7 @@ AArch64InstructionSelector::emitCSINC(Register Dst, Register Src1,
// If we used a register class, then this won't necessarily have an LLT.
// Compute the size based off whether or not we have a class or bank.
unsigned Size;
if (const auto *RC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>())
if (const auto *RC = dyn_cast<const TargetRegisterClass *>(RegClassOrBank))
Size = TRI.getRegSizeInBits(*RC);
else
Size = MRI.getType(Dst).getSizeInBits();
Expand Down
14 changes: 7 additions & 7 deletions llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
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Expand Up @@ -81,7 +81,7 @@ bool AMDGPUInstructionSelector::isVCC(Register Reg,

auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
const TargetRegisterClass *RC =
RegClassOrBank.dyn_cast<const TargetRegisterClass*>();
dyn_cast<const TargetRegisterClass *>(RegClassOrBank);
if (RC) {
const LLT Ty = MRI.getType(Reg);
if (!Ty.isValid() || Ty.getSizeInBits() != 1)
Expand All @@ -91,7 +91,7 @@ bool AMDGPUInstructionSelector::isVCC(Register Reg,
RC->hasSuperClassEq(TRI.getBoolRC());
}

const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>();
const RegisterBank *RB = cast<const RegisterBank *>(RegClassOrBank);
return RB->getID() == AMDGPU::VCCRegBankID;
}

Expand Down Expand Up @@ -233,15 +233,15 @@ bool AMDGPUInstructionSelector::selectPHI(MachineInstr &I) const {
const RegClassOrRegBank &RegClassOrBank =
MRI->getRegClassOrRegBank(DefReg);

const TargetRegisterClass *DefRC
= RegClassOrBank.dyn_cast<const TargetRegisterClass *>();
const TargetRegisterClass *DefRC =
dyn_cast<const TargetRegisterClass *>(RegClassOrBank);
if (!DefRC) {
if (!DefTy.isValid()) {
LLVM_DEBUG(dbgs() << "PHI operand has no type, not a gvreg?\n");
return false;
}

const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>();
const RegisterBank &RB = *cast<const RegisterBank *>(RegClassOrBank);
DefRC = TRI.getRegClassForTypeOnBank(DefTy, RB);
if (!DefRC) {
LLVM_DEBUG(dbgs() << "PHI operand has unexpected size/bank\n");
Expand Down Expand Up @@ -2395,11 +2395,11 @@ const RegisterBank *AMDGPUInstructionSelector::getArtifactRegBank(
Register Reg, const MachineRegisterInfo &MRI,
const TargetRegisterInfo &TRI) const {
const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
if (auto *RB = RegClassOrBank.dyn_cast<const RegisterBank *>())
if (auto *RB = dyn_cast<const RegisterBank *>(RegClassOrBank))
return RB;

// Ignore the type, since we don't use vcc in artifacts.
if (auto *RC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>())
if (auto *RC = dyn_cast<const TargetRegisterClass *>(RegClassOrBank))
return &RBI.getRegBankFromRegClass(*RC, LLT());
return nullptr;
}
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3682,10 +3682,10 @@ const TargetRegisterClass *
SIRegisterInfo::getConstrainedRegClassForOperand(const MachineOperand &MO,
const MachineRegisterInfo &MRI) const {
const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(MO.getReg());
if (const RegisterBank *RB = RCOrRB.dyn_cast<const RegisterBank*>())
if (const RegisterBank *RB = dyn_cast<const RegisterBank *>(RCOrRB))
return getRegClassForTypeOnBank(MRI.getType(MO.getReg()), *RB);

if (const auto *RC = RCOrRB.dyn_cast<const TargetRegisterClass *>())
if (const auto *RC = dyn_cast<const TargetRegisterClass *>(RCOrRB))
return getAllocatableClass(RC);

return nullptr;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp
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Expand Up @@ -303,7 +303,7 @@ static uint32_t calcArraySize(const DICompositeType *CTy, uint32_t StartDim) {
if (auto *Element = dyn_cast_or_null<DINode>(Elements[I]))
if (Element->getTag() == dwarf::DW_TAG_subrange_type) {
const DISubrange *SR = cast<DISubrange>(Element);
auto *CI = SR->getCount().dyn_cast<ConstantInt *>();
auto *CI = dyn_cast<ConstantInt *>(SR->getCount());
DimSize *= CI->getSExtValue();
}
}
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/BPF/BTFDebug.cpp
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Expand Up @@ -715,7 +715,7 @@ void BTFDebug::visitArrayType(const DICompositeType *CTy, uint32_t &TypeId) {
if (auto *Element = dyn_cast_or_null<DINode>(Elements[I]))
if (Element->getTag() == dwarf::DW_TAG_subrange_type) {
const DISubrange *SR = cast<DISubrange>(Element);
auto *CI = SR->getCount().dyn_cast<ConstantInt *>();
auto *CI = dyn_cast<ConstantInt *>(SR->getCount());
int64_t Count = CI->getSExtValue();

// For struct s { int b; char c[]; }, the c[] will be represented
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
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Expand Up @@ -598,14 +598,14 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
MRI->getRegClassOrRegBank(DefReg);

const TargetRegisterClass *DefRC =
RegClassOrBank.dyn_cast<const TargetRegisterClass *>();
dyn_cast<const TargetRegisterClass *>(RegClassOrBank);
if (!DefRC) {
if (!DefTy.isValid()) {
LLVM_DEBUG(dbgs() << "PHI operand has no type, not a gvreg?\n");
return false;
}

const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>();
const RegisterBank &RB = *cast<const RegisterBank *>(RegClassOrBank);
DefRC = getRegClassForTypeOnBank(DefTy, RB);
if (!DefRC) {
LLVM_DEBUG(dbgs() << "PHI operand has unexpected size/bank\n");
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp
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Expand Up @@ -141,8 +141,8 @@ yaml::WebAssemblyFunctionInfo::WebAssemblyFunctionInfo(
for (const auto &MBB : MF)
MBBs.insert(&MBB);
for (auto KV : EHInfo->SrcToUnwindDest) {
auto *SrcBB = KV.first.get<MachineBasicBlock *>();
auto *DestBB = KV.second.get<MachineBasicBlock *>();
auto *SrcBB = cast<MachineBasicBlock *>(KV.first);
auto *DestBB = cast<MachineBasicBlock *>(KV.second);
if (MBBs.count(SrcBB) && MBBs.count(DestBB))
SrcToUnwindDest[SrcBB->getNumber()] = DestBB->getNumber();
}
Expand Down
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