Skip to content
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
13 changes: 13 additions & 0 deletions llvm/tools/llvm-exegesis/lib/X86/Target.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -537,6 +537,8 @@ struct ConstantInliner {
std::vector<MCInst> loadImplicitRegAndFinalize(unsigned Opcode,
unsigned Value);

std::vector<MCInst> loadDirectionFlagAndFinalize();

private:
ConstantInliner &add(const MCInst &Inst) {
Instructions.push_back(Inst);
Expand Down Expand Up @@ -612,6 +614,15 @@ ConstantInliner::loadImplicitRegAndFinalize(unsigned Opcode, unsigned Value) {
return std::move(Instructions);
}

std::vector<MCInst> ConstantInliner::loadDirectionFlagAndFinalize() {
if (Constant_.isZero())
add(MCInstBuilder(X86::CLD));
else if (Constant_.isOne())
add(MCInstBuilder(X86::STD));

return std::move(Instructions);
}

void ConstantInliner::initStack(unsigned Bytes) {
assert(Constant_.getBitWidth() <= Bytes * 8 &&
"Value does not have the correct size");
Expand Down Expand Up @@ -1089,6 +1100,8 @@ std::vector<MCInst> ExegesisX86Target::setRegTo(const MCSubtargetInfo &STI,
0x1f80);
if (Reg == X86::FPCW)
return CI.loadImplicitRegAndFinalize(X86::FLDCW16m, 0x37f);
if (Reg == X86::DF)
return CI.loadDirectionFlagAndFinalize();
return {}; // Not yet implemented.
}

Expand Down
8 changes: 8 additions & 0 deletions llvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -585,6 +585,14 @@ TEST_F(X86Core2TargetTest, SetRegToFP1_4Bits) {
OpcodeIs(X86::LD_Fp80m), IsStackDeallocate(10)));
}

TEST_F(X86Core2TargetTest, SetRegToDf1) {
EXPECT_THAT(setRegTo(X86::DF, APInt(1, 1)), ElementsAre(OpcodeIs(X86::STD)));
}

TEST_F(X86Core2TargetTest, SetRegToDf0) {
EXPECT_THAT(setRegTo(X86::DF, APInt(1, 0)), ElementsAre(OpcodeIs(X86::CLD)));
}

TEST_F(X86Core2Avx512TargetTest, FillMemoryOperands_ADD64rm) {
const Instruction &I = getInstr(X86::ADD64rm);
InstructionTemplate IT(&I);
Expand Down
Loading