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[RISCV] Support svukte extension #115657

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Merged
merged 4 commits into from
Nov 27, 2024
Merged

[RISCV] Support svukte extension #115657

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0c95051
[RISCV] Support `svukte` extension
4vtomat Aug 5, 2024
86ba079
fixup! [RISCV] Support `svukte` extension
4vtomat Nov 19, 2024
4d7ab7f
fixup! [RISCV] Support `svukte` extension
4vtomat Nov 19, 2024
3cb5bb2
fixup! [RISCV] Support `svukte` extension
4vtomat Nov 26, 2024
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1 change: 1 addition & 0 deletions clang/test/Driver/print-supported-extensions-riscv.c
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Expand Up @@ -187,6 +187,7 @@
// CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)
// CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer Records Machine Level)
// CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level)
// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
// CHECK-EMPTY:
// CHECK-NEXT: Supported Profiles
// CHECK-NEXT: rva20s64
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8 changes: 8 additions & 0 deletions clang/test/Preprocessor/riscv-target-features.c
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Expand Up @@ -1811,6 +1811,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SSCTR-EXT %s
// CHECK-SSCTR-EXT: __riscv_ssctr 1000000{{$}}

// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_svukte0p3 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SVUKTE-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
// RUN: -march=rv64i_svukte0p3 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SVUKTE-EXT %s
// CHECK-SVUKTE-EXT: __riscv_svukte 3000{{$}}

// Misaligned

// RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32i -E -dM %s \
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1 change: 1 addition & 0 deletions llvm/docs/RISCVUsage.rst
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Expand Up @@ -158,6 +158,7 @@ on support follow.
``Svinval`` Assembly Support
``Svnapot`` Assembly Support
``Svpbmt`` Supported
``Svukte`` Supported
``Svvptc`` Supported
``V`` Supported
``Za128rs`` Supported (`See note <#riscv-profiles-extensions-note>`__)
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4 changes: 4 additions & 0 deletions llvm/lib/Target/RISCV/RISCVFeatures.td
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Expand Up @@ -1056,6 +1056,10 @@ def FeatureStdExtSha
FeatureStdExtShvstvala, FeatureStdExtShtvala, FeatureStdExtShvstvecd,
FeatureStdExtShvsatpa, FeatureStdExtShgatpa]>;

def FeatureStdExtSvukte
: RISCVExperimentalExtension<"svukte", 0, 3,
"'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)">;

// Pointer Masking extensions

// A supervisor-level extension that provides pointer masking for the next lower
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4 changes: 4 additions & 0 deletions llvm/test/CodeGen/RISCV/attributes.ll
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Expand Up @@ -62,6 +62,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+svbare %s -o - | FileCheck --check-prefixes=CHECK,RV32SVBARE %s
; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck --check-prefixes=CHECK,RV32SVNAPOT %s
; RUN: llc -mtriple=riscv32 -mattr=+svpbmt %s -o - | FileCheck --check-prefixes=CHECK,RV32SVPBMT %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-svukte %s -o - | FileCheck --check-prefixes=CHECK,RV32SVUKTE %s
; RUN: llc -mtriple=riscv32 -mattr=+svvptc %s -o - | FileCheck --check-prefixes=CHECK,RV32SVVPTC %s
; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV32SVINVAL %s
; RUN: llc -mtriple=riscv32 -mattr=+xcvalu %s -o - | FileCheck --check-prefix=RV32XCVALU %s
Expand Down Expand Up @@ -205,6 +206,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+svbare %s -o - | FileCheck --check-prefixes=CHECK,RV64SVBARE %s
; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefixes=CHECK,RV64SVNAPOT %s
; RUN: llc -mtriple=riscv64 -mattr=+svpbmt %s -o - | FileCheck --check-prefixes=CHECK,RV64SVPBMT %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-svukte %s -o - | FileCheck --check-prefixes=CHECK,RV64SVUKTE %s
; RUN: llc -mtriple=riscv64 -mattr=+svvptc %s -o - | FileCheck --check-prefixes=CHECK,RV64SVVPTC %s
; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV64SVINVAL %s
; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck --check-prefixes=CHECK,RV64XVENTANACONDOPS %s
Expand Down Expand Up @@ -364,6 +366,7 @@
; RV32SVBARE: .attribute 5, "rv32i2p1_svbare1p0"
; RV32SVNAPOT: .attribute 5, "rv32i2p1_svnapot1p0"
; RV32SVPBMT: .attribute 5, "rv32i2p1_svpbmt1p0"
; RV32SVUKTE: .attribute 5, "rv32i2p1_svukte0p3"
; RV32SVVPTC: .attribute 5, "rv32i2p1_svvptc1p0"
; RV32SVINVAL: .attribute 5, "rv32i2p1_svinval1p0"
; RV32XCVALU: .attribute 5, "rv32i2p1_xcvalu1p0"
Expand Down Expand Up @@ -509,6 +512,7 @@
; RV64SVBARE: .attribute 5, "rv64i2p1_svbare1p0"
; RV64SVNAPOT: .attribute 5, "rv64i2p1_svnapot1p0"
; RV64SVPBMT: .attribute 5, "rv64i2p1_svpbmt1p0"
; RV64SVUKTE: .attribute 5, "rv64i2p1_svukte0p3"
; RV64SVVPTC: .attribute 5, "rv64i2p1_svvptc1p0"
; RV64SVINVAL: .attribute 5, "rv64i2p1_svinval1p0"
; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p1_xventanacondops1p0"
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3 changes: 3 additions & 0 deletions llvm/test/MC/RISCV/attribute-arch.s
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Expand Up @@ -381,6 +381,9 @@
.attribute arch, "rv32i_svbare1p0"
# CHECK: attribute 5, "rv32i2p1_svbare1p0"

.attribute arch, "rv32i_svukte0p3"
# CHECK: attribute 5, "rv32i2p1_svukte0p3"

.attribute arch, "rv32i_svvptc1p0"
# CHECK: attribute 5, "rv32i2p1_svvptc1p0"

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1 change: 1 addition & 0 deletions llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
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Expand Up @@ -1094,6 +1094,7 @@ Experimental extensions
zvkgs 0.7
smctr 1.0
ssctr 1.0
svukte 0.3
Supported Profiles
rva20s64
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