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[SPIR-V] Disable Machine Sink pass in SPIR-V Backend #116060

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Merged
merged 1 commit into from
Nov 19, 2024
Merged

[SPIR-V] Disable Machine Sink pass in SPIR-V Backend #116060

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11 changes: 11 additions & 0 deletions llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -102,6 +102,7 @@ class SPIRVPassConfig : public TargetPassConfig {
SPIRVTargetMachine &getSPIRVTargetMachine() const {
return getTM<SPIRVTargetMachine>();
}
void addMachineSSAOptimization() override;
void addIRPasses() override;
void addISelPrepare() override;

Expand Down Expand Up @@ -129,6 +130,16 @@ FunctionPass *SPIRVPassConfig::createTargetRegisterAllocator(bool) {
return nullptr;
}

// Disable passes that may break CFG.
void SPIRVPassConfig::addMachineSSAOptimization() {
// Some standard passes that optimize machine instructions in SSA form uses
// MI.isPHI() that doesn't account for OpPhi in SPIR-V and so are able to
// break the CFG (e.g., MachineSink).
disablePass(&MachineSinkingID);

TargetPassConfig::addMachineSSAOptimization();
}

// Disable passes that break from assuming no virtual registers exist.
void SPIRVPassConfig::addPostRegAlloc() {
// Do not work with vregs instead of physical regs.
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