Skip to content

[SDAG][ISel][TableGen][LoongArch] Report error for trivial bitcasts when there are predicate calls #116075

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 3 commits into from
Nov 19, 2024
Merged

[SDAG][ISel][TableGen][LoongArch] Report error for trivial bitcasts when there are predicate calls #116075

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
7d1919b
[LoongArch] Add pre-commit tests. NFC.
dtcxzyw Nov 13, 2024
b048ebf
[SDAG][ISel][TableGen] Do not skip through bitcasts when there are pr…
dtcxzyw Nov 13, 2024
fe9ab8b
[SDAG][ISel][TableGen] Report error for trivial bitconvert node with …
dtcxzyw Nov 14, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
6 changes: 2 additions & 4 deletions llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -74,8 +74,7 @@ class VecCond<SDPatternOperator OpNode, ValueType TyNode,
let usesCustomInserter = 1;
}

def vsplat_imm_eq_1 : PatFrags<(ops), [(build_vector),
(bitconvert (v4i32 (build_vector)))], [{
def vsplat_imm_eq_1 : PatFrags<(ops), [(build_vector)], [{
APInt Imm;
EVT EltTy = N->getValueType(0).getVectorElementType();

Expand Down Expand Up @@ -116,8 +115,7 @@ def vsplati32_imm_eq_31 : PatFrags<(ops), [(build_vector)], [{
return selectVSplat(N, Imm, EltTy.getSizeInBits()) &&
Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 31;
}]>;
def vsplati64_imm_eq_63 : PatFrags<(ops), [(build_vector),
(bitconvert (v4i32 (build_vector)))], [{
def vsplati64_imm_eq_63 : PatFrags<(ops), [(build_vector)], [{
APInt Imm;
EVT EltTy = N->getValueType(0).getVectorElementType();

Expand Down
17 changes: 17 additions & 0 deletions llvm/test/CodeGen/LoongArch/lsx/pr116008.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,17 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s

define <4 x i32> @xor_shl_splat_vec_one(i32 %x, <4 x i32> %y) nounwind {
; CHECK-LABEL: xor_shl_splat_vec_one:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vreplgr2vr.w $vr1, $a0
; CHECK-NEXT: vsll.w $vr0, $vr1, $vr0
; CHECK-NEXT: vbitrevi.w $vr0, $vr0, 0
; CHECK-NEXT: ret
entry:
%ins = insertelement <4 x i32> poison, i32 %x, i64 0
%splat = shufflevector <4 x i32> %ins, <4 x i32> poison, <4 x i32> zeroinitializer
%shl = shl <4 x i32> %splat, %y
%xor = xor <4 x i32> %shl, splat (i32 1)
ret <4 x i32> %xor
}
8 changes: 8 additions & 0 deletions llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3056,6 +3056,14 @@ static bool SimplifyTree(TreePatternNodePtr &N) {
!N->getExtType(0).empty() &&
N->getExtType(0) == N->getChild(0).getExtType(0) &&
N->getName().empty()) {
if (!N->getPredicateCalls().empty()) {
std::string Str;
raw_string_ostream OS(Str);
OS << *N
<< "\n trivial bitconvert node should not have predicate calls\n";
PrintFatalError(Str);
return false;
}
N = N->getChildShared(0);
SimplifyTree(N);
return true;
Expand Down
Loading