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[X86][LLD] Handle R_X86_64_CODE_4_GOTTPOFF relocation type #116634

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Merged
merged 4 commits into from
Nov 27, 2024
Merged

[X86][LLD] Handle R_X86_64_CODE_4_GOTTPOFF relocation type #116634

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ea53c43
[X86][LLD] Handle R_X86_64_CODE_4_GOTTPOFF relocation type
fzou1 Nov 13, 2024
d1fdd48
Updated test, added comments and removed symbols unneeded.
fzou1 Nov 19, 2024
7b494f4
Updated for readability.
fzou1 Nov 23, 2024
4123725
Added early return for invalid prefix
fzou1 Nov 26, 2024
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87 changes: 56 additions & 31 deletions lld/ELF/Arch/X86_64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -396,6 +396,7 @@ RelExpr X86_64::getRelExpr(RelType type, const Symbol &s,
case R_X86_64_REX_GOTPCRELX:
case R_X86_64_CODE_4_GOTPCRELX:
case R_X86_64_GOTTPOFF:
case R_X86_64_CODE_4_GOTTPOFF:
return R_GOT_PC;
case R_X86_64_GOTOFF64:
return R_GOTPLTREL;
Expand Down Expand Up @@ -547,44 +548,66 @@ void X86_64::relaxTlsGdToIe(uint8_t *loc, const Relocation &rel,
}
}

// In some conditions, R_X86_64_GOTTPOFF relocation can be optimized to
// R_X86_64_TPOFF32 so that it does not use GOT.
// In some conditions, R_X86_64_GOTTPOFF/R_X86_64_CODE_4_GOTTPOFF relocation can
// be optimized to R_X86_64_TPOFF32 so that it does not use GOT.
void X86_64::relaxTlsIeToLe(uint8_t *loc, const Relocation &rel,
uint64_t val) const {
uint8_t *inst = loc - 3;
uint8_t reg = loc[-1] >> 3;
uint8_t *regSlot = loc - 1;

// Note that ADD with RSP or R12 is converted to ADD instead of LEA
// because LEA with these registers needs 4 bytes to encode and thus
// wouldn't fit the space.

if (memcmp(inst, "\x48\x03\x25", 3) == 0) {
// "addq foo@gottpoff(%rip),%rsp" -> "addq $foo,%rsp"
memcpy(inst, "\x48\x81\xc4", 3);
} else if (memcmp(inst, "\x4c\x03\x25", 3) == 0) {
// "addq foo@gottpoff(%rip),%r12" -> "addq $foo,%r12"
memcpy(inst, "\x49\x81\xc4", 3);
} else if (memcmp(inst, "\x4c\x03", 2) == 0) {
// "addq foo@gottpoff(%rip),%r[8-15]" -> "leaq foo(%r[8-15]),%r[8-15]"
memcpy(inst, "\x4d\x8d", 2);
*regSlot = 0x80 | (reg << 3) | reg;
} else if (memcmp(inst, "\x48\x03", 2) == 0) {
// "addq foo@gottpoff(%rip),%reg -> "leaq foo(%reg),%reg"
memcpy(inst, "\x48\x8d", 2);
*regSlot = 0x80 | (reg << 3) | reg;
} else if (memcmp(inst, "\x4c\x8b", 2) == 0) {
// "movq foo@gottpoff(%rip),%r[8-15]" -> "movq $foo,%r[8-15]"
memcpy(inst, "\x49\xc7", 2);
*regSlot = 0xc0 | reg;
} else if (memcmp(inst, "\x48\x8b", 2) == 0) {
// "movq foo@gottpoff(%rip),%reg" -> "movq $foo,%reg"
memcpy(inst, "\x48\xc7", 2);
*regSlot = 0xc0 | reg;
if (rel.type == R_X86_64_GOTTPOFF) {
// Note that ADD with RSP or R12 is converted to ADD instead of LEA
// because LEA with these registers needs 4 bytes to encode and thus
// wouldn't fit the space.

if (memcmp(inst, "\x48\x03\x25", 3) == 0) {
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@MaskRay MaskRay Nov 19, 2024

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This complexity is out of my depth. Hope that @KanRobert can verify it.

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@fzou1 fzou1 Nov 19, 2024

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This is the original code for handling R_X86_64_GOTPTOFF. I added another path below to handle R_X86_64_CODE_4_GOTPTOFF.

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@KanRobert KanRobert Nov 19, 2024

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I will try to check if after #116633, at that time, we can at least ensure that the existing rewrite is correct by LIT tests.

// "addq foo@gottpoff(%rip),%rsp" -> "addq $foo,%rsp"
memcpy(inst, "\x48\x81\xc4", 3);
} else if (memcmp(inst, "\x4c\x03\x25", 3) == 0) {
// "addq foo@gottpoff(%rip),%r12" -> "addq $foo,%r12"
memcpy(inst, "\x49\x81\xc4", 3);
} else if (memcmp(inst, "\x4c\x03", 2) == 0) {
// "addq foo@gottpoff(%rip),%r[8-15]" -> "leaq foo(%r[8-15]),%r[8-15]"
memcpy(inst, "\x4d\x8d", 2);
*regSlot = 0x80 | (reg << 3) | reg;
} else if (memcmp(inst, "\x48\x03", 2) == 0) {
// "addq foo@gottpoff(%rip),%reg -> "leaq foo(%reg),%reg"
memcpy(inst, "\x48\x8d", 2);
*regSlot = 0x80 | (reg << 3) | reg;
} else if (memcmp(inst, "\x4c\x8b", 2) == 0) {
// "movq foo@gottpoff(%rip),%r[8-15]" -> "movq $foo,%r[8-15]"
memcpy(inst, "\x49\xc7", 2);
*regSlot = 0xc0 | reg;
} else if (memcmp(inst, "\x48\x8b", 2) == 0) {
// "movq foo@gottpoff(%rip),%reg" -> "movq $foo,%reg"
memcpy(inst, "\x48\xc7", 2);
*regSlot = 0xc0 | reg;
} else {
Err(ctx)
<< getErrorLoc(ctx, loc - 3)
<< "R_X86_64_GOTTPOFF must be used in MOVQ or ADDQ instructions only";
}
} else {
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@KanRobert KanRobert Nov 23, 2024

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relaxTlsIeToLe is only called for R_X86_64_CODE_4_GOTTPOFF and R_X86_64_GOTTPOFF. Probably, the code can be more readable by removing the first assert below and use

else if (rel.type == R_X86_64_CODE_4_GOTTPOFF) {
} else {
  llvm_unreachable("Unsupported relocation type!")
 }
 
 And I think the following R_X86_64_CODE_6_GOTTPOFF support can benefit from this too. 
 
 The second `assert` should not be there, the diagnostic info should be always be reported by code like line 606

    Err(ctx) << getErrorLoc(ctx, loc - 3)
             << "R_X86_64_CODE_4_GOTTPOFF must be used in MOVQ or ADDQ "
                "instructions only";

, otherwise the error would be hidden in the release build.  BTW,  it seems `loc - 4` should be used here.

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@fzou1 fzou1 Nov 23, 2024

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Done. Thanks.

ErrAlways(ctx)
<< getErrorLoc(ctx, loc - 3)
<< "R_X86_64_GOTTPOFF must be used in MOVQ or ADDQ instructions only";
assert(rel.type == R_X86_64_CODE_4_GOTTPOFF &&
"Unsupported relocation type!");
assert((loc[-4] == 0xd5) &&
"Invalid prefix with R_X86_64_CODE_4_GOTTPOFF!");
const uint8_t rex = loc[-3];
loc[-3] = (rex & ~0x44) | (rex & 0x44) >> 2;
*regSlot = 0xc0 | reg;

// "movq foo@gottpoff(%rip),%r[16-31]" -> "movq $foo,%r[16-31]"
if (loc[-2] == 0x8b)
loc[-2] = 0xc7;
else {
// "addq foo@gottpoff(%rip),%r[16-31]" -> "addq $foo,%r[16-31]"
if (loc[-2] != 0x03)
Err(ctx) << getErrorLoc(ctx, loc - 3)
<< "R_X86_64_CODE_4_GOTTPOFF must be used in MOVQ or ADDQ "
"instructions only";
loc[-2] = 0x81;
}
}

// The original code used a PC relative relocation.
Expand Down Expand Up @@ -741,6 +764,7 @@ int64_t X86_64::getImplicitAddend(const uint8_t *buf, RelType type) const {
case R_X86_64_CODE_4_GOTPCRELX:
case R_X86_64_PC32:
case R_X86_64_GOTTPOFF:
case R_X86_64_CODE_4_GOTTPOFF:
case R_X86_64_PLT32:
case R_X86_64_TLSGD:
case R_X86_64_TLSLD:
Expand Down Expand Up @@ -850,6 +874,7 @@ void X86_64::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
}
break;
case R_X86_64_GOTTPOFF:
case R_X86_64_CODE_4_GOTTPOFF:
if (rel.expr == R_RELAX_TLS_IE_TO_LE) {
relaxTlsIeToLe(loc, rel, val);
} else {
Expand Down
6 changes: 5 additions & 1 deletion lld/test/ELF/pack-dyn-relocs-tls-x86-64.s
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Original file line number Diff line number Diff line change
Expand Up @@ -12,12 +12,16 @@
.globl foo
foo:
movq tlsvar@GOTTPOFF(%rip), %rcx
movq tlsvar2@GOTTPOFF(%rip), %r31


.section .tdata,"awT",@progbits
.space 0x1234
tlsvar:
.word 42

tlsvar2:
.word 42
// CHECK: Section ({{.+}}) .rela.dyn {
// CHECK-NEXT: R_X86_64_TPOFF64 - 0x1234
// CHECK-NEXT: R_X86_64_TPOFF64 - 0x1236
// CHECK-NEXT: }
13 changes: 13 additions & 0 deletions lld/test/ELF/tls-opt.s
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Expand Up @@ -20,6 +20,12 @@
// DISASM-NEXT: leaq -4(%r15), %r15
// DISASM-NEXT: addq $-4, %rsp
// DISASM-NEXT: addq $-4, %r12
// DISASM-NEXT: movq $-8, %r16
// DISASM-NEXT: movq $-8, %r20
// DISASM-NEXT: movq $-4, %r16
// DISASM-NEXT: addq $-8, %r16
// DISASM-NEXT: addq $-8, %r28
// DISASM-NEXT: addq $-4, %r16

// LD to LE:
// DISASM-NEXT: movq %fs:0, %rax
Expand Down Expand Up @@ -69,6 +75,13 @@ _start:
addq tls1@GOTTPOFF(%rip), %r15
addq tls1@GOTTPOFF(%rip), %rsp
addq tls1@GOTTPOFF(%rip), %r12
# EGPR
movq tls0@GOTTPOFF(%rip), %r16
movq tls0@GOTTPOFF(%rip), %r20
movq tls1@GOTTPOFF(%rip), %r16
addq tls0@GOTTPOFF(%rip), %r16
addq tls0@GOTTPOFF(%rip), %r28
addq tls1@GOTTPOFF(%rip), %r16

// LD to LE
leaq tls0@tlsld(%rip), %rdi
Expand Down
22 changes: 15 additions & 7 deletions lld/test/ELF/x86-64-tls-ie-local.s
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Expand Up @@ -5,21 +5,29 @@
# RUN: llvm-readobj -r %t.so | FileCheck --check-prefix=REL %s
# RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn %t.so | FileCheck %s

# SEC: .got PROGBITS 0000000000002338 000338 000010 00 WA 0 0 8
# SEC: .got PROGBITS 0000000000002348 000348 000010 00 WA 0 0 8

## Dynamic relocations for non-preemptable symbols in a shared object have section index 0.
# REL: .rela.dyn {
# REL-NEXT: 0x2338 R_X86_64_TPOFF64 - 0x0
# REL-NEXT: 0x2340 R_X86_64_TPOFF64 - 0x4
# REL-NEXT: 0x2348 R_X86_64_TPOFF64 - 0x0
# REL-NEXT: 0x2350 R_X86_64_TPOFF64 - 0x4
# REL-NEXT: }

## &.got[0] - 0x127f = 0x2338 - 0x127f = 4281
## &.got[1] - 0x1286 = 0x2340 - 0x1286 = 4282
# CHECK: 1278: addq 4281(%rip), %rax
# CHECK-NEXT: 127f: addq 4282(%rip), %rax
## &.got[0] - 0x127f = 0x2348 - 0x127f = 4297
## &.got[1] - 0x1286 = 0x2350 - 0x1286 = 4298
## &.got[2] - 0x128e = 0x2348 - 0x128e = 4282
## &.got[3] - 0x1296 = 0x2350 - 0x1296 = 4282

# CHECK: 1278: addq 4297(%rip), %rax
# CHECK-NEXT: 127f: addq 4298(%rip), %rax
# CHECK-NEXT: 1286: addq 4282(%rip), %r16
# CHECK-NEXT: 128e: addq 4282(%rip), %r16

addq foo@GOTTPOFF(%rip), %rax
addq bar@GOTTPOFF(%rip), %rax
addq foo@GOTTPOFF(%rip), %r16
addq bar@GOTTPOFF(%rip), %r16


.section .tbss,"awT",@nobits
foo:
Expand Down
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