[RISCV] Fix FP64 DinX R Regclass

[lenary]

This was a typo in #112983 that didn't cause build failures but is still wrong.

---

I have half a PR to merge the GPR and GPRF64 classes, but this should go in before that (rebasing that PR is how I noticed this problem)

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: Sam Elliott (lenary)

Changes

This was a typo in llvm/llvm-project#112983 that didn't cause build failures but is still wrong.

---

I have half a PR to merge the GPR and GPRF64 classes, but this should go in before that (rebasing that PR is how I noticed this problem)

---

Full diff: https://github.com/llvm/llvm-project/pull/116688.diff

1 Files Affected:

• (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+1-1)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 35040734d71dfa..556b337da4d68f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -20531,7 +20531,7 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
       break;
     case 'R':
       if (VT == MVT::f64 && !Subtarget.is64Bit() && Subtarget.hasStdExtZdinx())
-        return std::make_pair(0U, &RISCV::GPRF64PairCRegClass);
+        return std::make_pair(0U, &RISCV::GPRF64PairNoX0RegClass);
       return std::make_pair(0U, &RISCV::GPRPairNoX0RegClass);
     default:
       break;

[topperc]

LGTM

[lenary]

I missed that this changed the allocation in the test. I'm going to merge with the test I just fixed.