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[LoongArch] Support LA V1.1 feature that div.w[u] and mod.w[u] instructions with inputs not signed-extended. #116764
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[LoongArch] Support LA V1.1 feature that div.w[u] and mod.w[u] instru…
tangaac 1d0477f
add a test
tangaac b2bc7fa
remove uncessary ir attributes
tangaac 97dcea3
remove LoongArchISD:{DIV_W,MOD_W} , add div32 support in sys::getHost…
tangaac 20c9378
add a todo comment
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,30 @@ | ||
| /// Test -m[no]div32 options. | ||
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| // RUN: %clang --target=loongarch64 -mdiv32 -fsyntax-only %s -### 2>&1 | \ | ||
| // RUN: FileCheck %s --check-prefix=CC1-DIV32 | ||
| // RUN: %clang --target=loongarch64 -mno-div32 -fsyntax-only %s -### 2>&1 | \ | ||
| // RUN: FileCheck %s --check-prefix=CC1-NO-DIV32 | ||
| // RUN: %clang --target=loongarch64 -mno-div32 -mdiv32 -fsyntax-only %s -### 2>&1 | \ | ||
| // RUN: FileCheck %s --check-prefix=CC1-DIV32 | ||
| // RUN: %clang --target=loongarch64 -mdiv32 -mno-div32 -fsyntax-only %s -### 2>&1 | \ | ||
| // RUN: FileCheck %s --check-prefix=CC1-NO-DIV32 | ||
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| // RUN: %clang --target=loongarch64 -mdiv32 -S -emit-llvm %s -o - | \ | ||
| // RUN: FileCheck %s --check-prefix=IR-DIV32 | ||
| // RUN: %clang --target=loongarch64 -mno-div32 -S -emit-llvm %s -o - | \ | ||
| // RUN: FileCheck %s --check-prefix=IR-NO-DIV32 | ||
| // RUN: %clang --target=loongarch64 -mno-div32 -mdiv32 -S -emit-llvm %s -o - | \ | ||
| // RUN: FileCheck %s --check-prefix=IR-DIV32 | ||
| // RUN: %clang --target=loongarch64 -mdiv32 -mno-div32 -S -emit-llvm %s -o - | \ | ||
| // RUN: FileCheck %s --check-prefix=IR-NO-DIV32 | ||
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| // CC1-DIV32: "-target-feature" "+div32" | ||
| // CC1-NO-DIV32: "-target-feature" "-div32" | ||
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| // IR-DIV32: attributes #[[#]] ={{.*}}"target-features"="{{(.*,)?}}+div32{{(,.*)?}}" | ||
| // IR-NO-DIV32: attributes #[[#]] ={{.*}}"target-features"="{{(.*,)?}}-div32{{(,.*)?}}" | ||
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| int foo(void) { | ||
| return 42; | ||
| } |
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81 changes: 81 additions & 0 deletions
81
llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem-div32.ll
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,81 @@ | ||
| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py | ||
| ; RUN: llc --mtriple=loongarch64 -mattr=+d,-div32 < %s | FileCheck %s --check-prefix=LA64 | ||
| ; RUN: llc --mtriple=loongarch64 -mattr=+d,+div32 < %s | FileCheck %s --check-prefix=LA64-DIV32 | ||
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| ; TODO: Use div.w/mod.w for sdiv/srem i32 | ||
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| define i32 @divw(i64 %a, i64 %b) { | ||
| ; LA64-LABEL: divw: | ||
| ; LA64: # %bb.0: | ||
| ; LA64-NEXT: addi.w $a0, $a0, 0 | ||
| ; LA64-NEXT: addi.w $a1, $a1, 0 | ||
| ; LA64-NEXT: div.d $a0, $a0, $a1 | ||
| ; LA64-NEXT: ret | ||
| ; | ||
| ; LA64-DIV32-LABEL: divw: | ||
| ; LA64-DIV32: # %bb.0: | ||
| ; LA64-DIV32-NEXT: addi.w $a0, $a0, 0 | ||
| ; LA64-DIV32-NEXT: addi.w $a1, $a1, 0 | ||
| ; LA64-DIV32-NEXT: div.d $a0, $a0, $a1 | ||
| ; LA64-DIV32-NEXT: ret | ||
| %conv1 = trunc i64 %a to i32 | ||
| %conv2 = trunc i64 %b to i32 | ||
| %r = sdiv i32 %conv1, %conv2 | ||
| ret i32 %r | ||
| } | ||
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| define i32 @divwu(i64 %a, i64 %b) { | ||
| ; LA64-LABEL: divwu: | ||
| ; LA64: # %bb.0: | ||
| ; LA64-NEXT: addi.w $a1, $a1, 0 | ||
| ; LA64-NEXT: addi.w $a0, $a0, 0 | ||
| ; LA64-NEXT: div.wu $a0, $a0, $a1 | ||
| ; LA64-NEXT: ret | ||
| ; | ||
| ; LA64-DIV32-LABEL: divwu: | ||
| ; LA64-DIV32: # %bb.0: | ||
| ; LA64-DIV32-NEXT: div.wu $a0, $a0, $a1 | ||
| ; LA64-DIV32-NEXT: ret | ||
| %conv1 = trunc i64 %a to i32 | ||
| %conv2 = trunc i64 %b to i32 | ||
| %r = udiv i32 %conv1, %conv2 | ||
| ret i32 %r | ||
| } | ||
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| define i32 @modw(i64 %a, i64 %b) { | ||
| ; LA64-LABEL: modw: | ||
| ; LA64: # %bb.0: | ||
| ; LA64-NEXT: addi.w $a0, $a0, 0 | ||
| ; LA64-NEXT: addi.w $a1, $a1, 0 | ||
| ; LA64-NEXT: mod.d $a0, $a0, $a1 | ||
| ; LA64-NEXT: ret | ||
| ; | ||
| ; LA64-DIV32-LABEL: modw: | ||
| ; LA64-DIV32: # %bb.0: | ||
| ; LA64-DIV32-NEXT: addi.w $a0, $a0, 0 | ||
| ; LA64-DIV32-NEXT: addi.w $a1, $a1, 0 | ||
| ; LA64-DIV32-NEXT: mod.d $a0, $a0, $a1 | ||
| ; LA64-DIV32-NEXT: ret | ||
| %conv1 = trunc i64 %a to i32 | ||
| %conv2 = trunc i64 %b to i32 | ||
| %r = srem i32 %conv1, %conv2 | ||
| ret i32 %r | ||
| } | ||
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| define i32 @modwu(i64 %a, i64 %b) { | ||
| ; LA64-LABEL: modwu: | ||
| ; LA64: # %bb.0: | ||
| ; LA64-NEXT: addi.w $a1, $a1, 0 | ||
| ; LA64-NEXT: addi.w $a0, $a0, 0 | ||
| ; LA64-NEXT: mod.wu $a0, $a0, $a1 | ||
| ; LA64-NEXT: ret | ||
| ; | ||
| ; LA64-DIV32-LABEL: modwu: | ||
| ; LA64-DIV32: # %bb.0: | ||
| ; LA64-DIV32-NEXT: mod.wu $a0, $a0, $a1 | ||
| ; LA64-DIV32-NEXT: ret | ||
| %conv1 = trunc i64 %a to i32 | ||
| %conv2 = trunc i64 %b to i32 | ||
| %r = urem i32 %conv1, %conv2 | ||
| ret i32 %r | ||
| } | ||
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TODOhere that the issue will be addressed by another PR.