[SDAG] [X86] Extend SplitVecOp_VSETCC for STRICT_FSETCCS

[abhishek-kaushik22]

Closes #116767

[llvmbot]

@llvm/pr-subscribers-llvm-selectiondag

@llvm/pr-subscribers-backend-x86

Author: None (abhishek-kaushik22)

Changes

Closes #116767

---

Full diff: https://github.com/llvm/llvm-project/pull/116768.diff

2 Files Affected:

• (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (+7-4)
• (added) llvm/test/CodeGen/X86/vec-strict-cmp-512-skx-fp64.ll (+31)

diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index eccda73548e874..3dda807ed65259 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -3235,6 +3235,7 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
 
   case ISD::VP_SETCC:
   case ISD::STRICT_FSETCC:
+  case ISD::STRICT_FSETCCS:
   case ISD::SETCC:             Res = SplitVecOp_VSETCC(N); break;
   case ISD::BITCAST:           Res = SplitVecOp_BITCAST(N); break;
   case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
@@ -4236,7 +4237,8 @@ SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) {
 }
 
 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
-  bool isStrict = N->getOpcode() == ISD::STRICT_FSETCC;
+  bool isStrict = N->getOpcode() == ISD::STRICT_FSETCC ||
+                  N->getOpcode() == ISD::STRICT_FSETCCS;
   assert(N->getValueType(0).isVector() &&
          N->getOperand(isStrict ? 1 : 0).getValueType().isVector() &&
          "Operand types must be vectors");
@@ -4255,11 +4257,12 @@ SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
   if (N->getOpcode() == ISD::SETCC) {
     LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
     HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
-  } else if (N->getOpcode() == ISD::STRICT_FSETCC) {
-    LoRes = DAG.getNode(ISD::STRICT_FSETCC, DL,
+  } else if (N->getOpcode() == ISD::STRICT_FSETCC ||
+             N->getOpcode() == ISD::STRICT_FSETCCS) {
+    LoRes = DAG.getNode(N->getOpcode(), DL,
                         DAG.getVTList(PartResVT, N->getValueType(1)),
                         N->getOperand(0), Lo0, Lo1, N->getOperand(3));
-    HiRes = DAG.getNode(ISD::STRICT_FSETCC, DL,
+    HiRes = DAG.getNode(N->getOpcode(), DL,
                         DAG.getVTList(PartResVT, N->getValueType(1)),
                         N->getOperand(0), Hi0, Hi1, N->getOperand(3));
     SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
diff --git a/llvm/test/CodeGen/X86/vec-strict-cmp-512-skx-fp64.ll b/llvm/test/CodeGen/X86/vec-strict-cmp-512-skx-fp64.ll
new file mode 100644
index 00000000000000..c3d4052c553f59
--- /dev/null
+++ b/llvm/test/CodeGen/X86/vec-strict-cmp-512-skx-fp64.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s -mtriple=x86_64 -mcpu=skx | FileCheck %s --check-prefixes=SKX
+
+define <16 x i32> @test_v16f64_ogt(<16 x i32> %a, <16 x i32> %b, <16 x double> %f1, <16 x double> %f2) #0 {
+; SKX-LABEL: test_v16f64_ogt
+; SKX:       # %bb.0:
+; SKX-NEXT:  pushq	%rbp
+; SKX-NEXT:  movq	%rsp, %rbp
+; SKX-NEXT:  andq	$-32, %rsp
+; SKX-NEXT:  subq	$32, %rsp
+; SKX-NEXT:  vcmpgtpd	80(%rbp), %ymm6, %k0
+; SKX-NEXT:  vcmpgtpd	112(%rbp), %ymm7, %k1
+; SKX-NEXT:  kshiftlb	$4, %k1, %k1
+; SKX-NEXT:  korb	%k1, %k0, %k1
+; SKX-NEXT:  vcmpgtpd	16(%rbp), %ymm4, %k0
+; SKX-NEXT:  vcmpgtpd	48(%rbp), %ymm5, %k2
+; SKX-NEXT:  kshiftlb	$4, %k2, %k2
+; SKX-NEXT:  korb	%k2, %k0, %k2
+; SKX-NEXT:  vpblendmd	%ymm0, %ymm2, %ymm0 {%k2}
+; SKX-NEXT:  vpblendmd	%ymm1, %ymm3, %ymm1 {%k1}
+; SKX-NEXT:  movq	%rbp, %rsp
+; SKX-NEXT:  popq	%rbp
+; SKX-NEXT:  retq
+  %cond = tail call <16 x i1> @llvm.experimental.constrained.fcmps.v16f64(
+    <16 x double> %f1, <16 x double> %f2, metadata !"ogt", metadata !"fpexcept.maytrap")
+  %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+  ret <16 x i32> %res
+}
+
+declare <16 x i1> @llvm.experimental.constrained.fcmps.v16f64(<16 x double>, <16 x double>, metadata, metadata)
+
+attributes #0 = { nounwind strictfp "min-legal-vector-width"="0" }

[abhishek-kaushik22]

@MalaySanghi @phoebewang @e-kud Can you please review?

[MalaySanghi]

LGTM

[phoebewang]

LGTM.

[github-actions]

✅ With the latest revision this PR passed the C/C++ code formatter.

[e-kud]

LGTM. However I don't see any successful build. Maybe a merge from main is required?

[topperc]

LGTM

[abhishek-kaushik22]

Can someone please merge?