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[AArch64] Generate zeroing forms of certain SVE2.2 instructions (9/11) #116835

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Merged
momchil-velikov merged 2 commits into from
Jan 27, 2025
Merged

[AArch64] Generate zeroing forms of certain SVE2.2 instructions (9/11) #116835

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1d56344
[AArch64] Generate zeroing forms of certain SVE2.2 instructions (9/11)
momchil-velikov Nov 19, 2024
c54760e
[fixup] Rebase, update tests, add tests for the new all-true patterns…
momchil-velikov Dec 20, 2024
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8 changes: 4 additions & 4 deletions llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -4283,10 +4283,10 @@ let Predicates = [HasSVE2p2orSME2p2] in {
defm FLOGB_ZPzZ : sve_fp_z2op_p_zd_d_flogb<"flogb">;

// SVE2 integer unary operations, zeroing predicate
def URECPE_ZPzZ : sve2_int_un_pred_arit_z<0b10, 0b00, "urecpe", ZPR32>;
def URSQRTE_ZPzZ : sve2_int_un_pred_arit_z<0b10, 0b01, "ursqrte", ZPR32>;
defm SQABS_ZPzZ : sve2_int_un_pred_arit_z<0b10, "sqabs">;
defm SQNEG_ZPzZ : sve2_int_un_pred_arit_z<0b11, "sqneg">;
defm URECPE_ZPzZ : sve2_int_un_pred_arit_z_S<0b00, "urecpe", int_aarch64_sve_urecpe>;
defm URSQRTE_ZPzZ : sve2_int_un_pred_arit_z_S<0b01, "ursqrte", int_aarch64_sve_ursqrte>;
defm SQABS_ZPzZ : sve2_int_un_pred_arit_z< 0b10, "sqabs", int_aarch64_sve_sqabs>;
defm SQNEG_ZPzZ : sve2_int_un_pred_arit_z< 0b11, "sqneg", int_aarch64_sve_sqneg>;

// Floating point round to integral fp value in integer size range
// Merging
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13 changes: 12 additions & 1 deletion llvm/lib/Target/AArch64/SVEInstrFormats.td
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Expand Up @@ -4180,11 +4180,22 @@ multiclass sve2_int_un_pred_arit<bits<2> opc, string asm, SDPatternOperator op>
defm : SVE_3_Op_Undef_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2i64, !cast<Pseudo>(NAME # _D_UNDEF)>;
}

multiclass sve2_int_un_pred_arit_z<bits<2> opc, string asm> {
multiclass sve2_int_un_pred_arit_z_S<bits<2> opc, string asm, SDPatternOperator op> {
def _S : sve2_int_un_pred_arit_z<0b10, opc, asm, ZPR32>;

defm : SVE_3_Op_UndefZero_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
}

multiclass sve2_int_un_pred_arit_z<bits<2> opc, string asm, SDPatternOperator op> {
def _B : sve2_int_un_pred_arit_z<0b00, opc, asm, ZPR8>;
def _H : sve2_int_un_pred_arit_z<0b01, opc, asm, ZPR16>;
def _S : sve2_int_un_pred_arit_z<0b10, opc, asm, ZPR32>;
def _D : sve2_int_un_pred_arit_z<0b11, opc, asm, ZPR64>;

defm : SVE_3_Op_UndefZero_Pat<nxv16i8, op, nxv16i8, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>;
defm : SVE_3_Op_UndefZero_Pat<nxv8i16, op, nxv8i16, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H)>;
defm : SVE_3_Op_UndefZero_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
defm : SVE_3_Op_UndefZero_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
}

//===----------------------------------------------------------------------===//
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