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[AArch64] Generate zeroing forms of certain SVE2.2 instructions (10/11) #116836

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momchil-velikov merged 2 commits into from
Jan 27, 2025
Merged

[AArch64] Generate zeroing forms of certain SVE2.2 instructions (10/11) #116836

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3075771
[AArch64] Generate zeroing forms of certain SVE2.2 instructions (10/11)
momchil-velikov Nov 19, 2024
3cb1299
[fixup] Rebase, update tests, add tests for the new all-true patterns…
momchil-velikov Dec 20, 2024
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10 changes: 5 additions & 5 deletions llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -4339,11 +4339,11 @@ let Predicates = [HasSVE2p2orSME2p2] in {
defm LASTP_XPP : sve_int_pcount_pred_tmp<0b010, "lastp">;

// SVE reverse within elements, zeroing predicate
defm RBIT_ZPzZ : sve_int_perm_rev_rbit_z<"rbit">;
defm REVB_ZPzZ : sve_int_perm_rev_revb_z<"revb">;
defm REVH_ZPzZ : sve_int_perm_rev_revh_z<"revh">;
def REVW_ZPzZ : sve_int_perm_rev_z<0b11, 0b0110, "revw", ZPR64>;
def REVD_ZPzZ : sve_int_perm_rev_z<0b00, 0b1110, "revd", ZPR128>;
defm RBIT_ZPzZ : sve_int_perm_rev_rbit_z<"rbit", AArch64rbit_mt>;
defm REVB_ZPzZ : sve_int_perm_rev_revb_z<"revb", AArch64revb_mt>;
defm REVH_ZPzZ : sve_int_perm_rev_revh_z<"revh", AArch64revh_mt>;
defm REVW_ZPzZ : sve_int_perm_rev_revw_z<"revw", AArch64revw_mt>;
defm REVD_ZPzZ : sve_int_perm_rev_revd_z<"revd", AArch64revd_mt>;
} // End HasSME2p2orSVE2p2

//===----------------------------------------------------------------------===//
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38 changes: 35 additions & 3 deletions llvm/lib/Target/AArch64/SVEInstrFormats.td
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Expand Up @@ -7621,22 +7621,54 @@ class sve_int_perm_rev_z<bits<2> sz, bits<4> opc, string asm,
let hasSideEffects = 0;
}

multiclass sve_int_perm_rev_rbit_z<string asm> {
multiclass sve_int_perm_rev_rbit_z<string asm, SDPatternOperator op> {
def _B : sve_int_perm_rev_z<0b00, 0b0111, asm, ZPR8>;
def _H : sve_int_perm_rev_z<0b01, 0b0111, asm, ZPR16>;
def _S : sve_int_perm_rev_z<0b10, 0b0111, asm, ZPR32>;
def _D : sve_int_perm_rev_z<0b11, 0b0111, asm, ZPR64>;

defm : SVE_1_Op_PassthruUndefZero_Pat<nxv16i8, op, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>;
defm : SVE_1_Op_PassthruUndefZero_Pat<nxv8i16, op, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H)>;
defm : SVE_1_Op_PassthruUndefZero_Pat<nxv4i32, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
defm : SVE_1_Op_PassthruUndefZero_Pat<nxv2i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
}

multiclass sve_int_perm_rev_revb_z<string asm> {
multiclass sve_int_perm_rev_revb_z<string asm, SDPatternOperator op> {
def _H : sve_int_perm_rev_z<0b01, 0b0100, asm, ZPR16>;
def _S : sve_int_perm_rev_z<0b10, 0b0100, asm, ZPR32>;
def _D : sve_int_perm_rev_z<0b11, 0b0100, asm, ZPR64>;

defm : SVE_1_Op_PassthruUndefZero_Pat<nxv8i16, op, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H)>;
defm : SVE_1_Op_PassthruUndefZero_Pat<nxv4i32, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
defm : SVE_1_Op_PassthruUndefZero_Pat<nxv2i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
}

multiclass sve_int_perm_rev_revh_z<string asm> {
multiclass sve_int_perm_rev_revh_z<string asm, SDPatternOperator op> {
def _S : sve_int_perm_rev_z<0b10, 0b0101, asm, ZPR32>;
def _D : sve_int_perm_rev_z<0b11, 0b0101, asm, ZPR64>;

defm : SVE_1_Op_PassthruUndefZero_Pat<nxv4i32, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
defm : SVE_1_Op_PassthruUndefZero_Pat<nxv2i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
}

multiclass sve_int_perm_rev_revw_z<string asm, SDPatternOperator op> {
def _D : sve_int_perm_rev_z<0b11, 0b0110, asm, ZPR64>;

defm : SVE_1_Op_PassthruUndefZero_Pat<nxv2i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
}

multiclass sve_int_perm_rev_revd_z<string asm, SDPatternOperator op> {
def NAME : sve_int_perm_rev_z<0b00, 0b1110, asm, ZPR128>;

defm : SVE_1_Op_PassthruUndefZero_Pat<nxv16i8, op, nxv16i1, nxv16i8, !cast<Instruction>(NAME)>;
defm : SVE_1_Op_PassthruUndefZero_Pat<nxv8i16, op, nxv8i1, nxv8i16, !cast<Instruction>(NAME)>;
defm : SVE_1_Op_PassthruUndefZero_Pat<nxv4i32, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME)>;
defm : SVE_1_Op_PassthruUndefZero_Pat<nxv2i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME)>;

defm : SVE_1_Op_PassthruUndefZero_Pat<nxv8bf16, op, nxv8i1, nxv8bf16, !cast<Instruction>(NAME)>;
defm : SVE_1_Op_PassthruUndefZero_Pat<nxv8f16, op, nxv8i1, nxv8f16, !cast<Instruction>(NAME)>;
defm : SVE_1_Op_PassthruUndefZero_Pat<nxv4f32, op, nxv4i1, nxv4f32, !cast<Instruction>(NAME)>;
defm : SVE_1_Op_PassthruUndefZero_Pat<nxv2f64, op, nxv2i1, nxv2f64, !cast<Instruction>(NAME)>;
}

class sve_int_perm_cpy_r<bits<2> sz8_64, string asm, ZPRRegOp zprty,
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