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[LLVM][IR] Use splat syntax when printing ConstantExpr based splats. #116856

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Nov 21, 2024
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[LLVM][IR] Use splat syntax when printing ConstantExpr based splats. #116856

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554e49b
[LLVM][IR] Use splat syntax when printing ConstantExpr based splats.
paulwalker-arm Nov 19, 2024
519968e
Regenerate CHECK lines.
paulwalker-arm Nov 19, 2024
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36 changes: 18 additions & 18 deletions clang/test/CodeGen/AArch64/sve-vector-bitwise-ops.c
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Expand Up @@ -260,80 +260,80 @@ svuint64_t xor_u64(svuint64_t a, svuint64_t b) {

// CHECK-LABEL: @neg_bool(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[NEG:%.*]] = xor <vscale x 16 x i1> [[A:%.*]], shufflevector (<vscale x 16 x i1> insertelement (<vscale x 16 x i1> poison, i1 true, i64 0), <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer)
// CHECK-NEXT: ret <vscale x 16 x i1> [[NEG]]
// CHECK-NEXT: [[NOT:%.*]] = xor <vscale x 16 x i1> [[A:%.*]], splat (i1 true)
// CHECK-NEXT: ret <vscale x 16 x i1> [[NOT]]
//
svbool_t neg_bool(svbool_t a) {
return ~a;
}

// CHECK-LABEL: @neg_i8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[NEG:%.*]] = xor <vscale x 16 x i8> [[A:%.*]], shufflevector (<vscale x 16 x i8> insertelement (<vscale x 16 x i8> poison, i8 -1, i64 0), <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer)
// CHECK-NEXT: ret <vscale x 16 x i8> [[NEG]]
// CHECK-NEXT: [[NOT:%.*]] = xor <vscale x 16 x i8> [[A:%.*]], splat (i8 -1)
// CHECK-NEXT: ret <vscale x 16 x i8> [[NOT]]
//
svint8_t neg_i8(svint8_t a) {
return ~a;
}

// CHECK-LABEL: @neg_i16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[NEG:%.*]] = xor <vscale x 8 x i16> [[A:%.*]], shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> poison, i16 -1, i64 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer)
// CHECK-NEXT: ret <vscale x 8 x i16> [[NEG]]
// CHECK-NEXT: [[NOT:%.*]] = xor <vscale x 8 x i16> [[A:%.*]], splat (i16 -1)
// CHECK-NEXT: ret <vscale x 8 x i16> [[NOT]]
//
svint16_t neg_i16(svint16_t a) {
return ~a;
}

// CHECK-LABEL: @neg_i32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[NEG:%.*]] = xor <vscale x 4 x i32> [[A:%.*]], shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 -1, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
// CHECK-NEXT: ret <vscale x 4 x i32> [[NEG]]
// CHECK-NEXT: [[NOT:%.*]] = xor <vscale x 4 x i32> [[A:%.*]], splat (i32 -1)
// CHECK-NEXT: ret <vscale x 4 x i32> [[NOT]]
//
svint32_t neg_i32(svint32_t a) {
return ~a;
}

// CHECK-LABEL: @neg_i64(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[NEG:%.*]] = xor <vscale x 2 x i64> [[A:%.*]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 -1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
// CHECK-NEXT: ret <vscale x 2 x i64> [[NEG]]
// CHECK-NEXT: [[NOT:%.*]] = xor <vscale x 2 x i64> [[A:%.*]], splat (i64 -1)
// CHECK-NEXT: ret <vscale x 2 x i64> [[NOT]]
//
svint64_t neg_i64(svint64_t a) {
return ~a;
}

// CHECK-LABEL: @neg_u8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[NEG:%.*]] = xor <vscale x 16 x i8> [[A:%.*]], shufflevector (<vscale x 16 x i8> insertelement (<vscale x 16 x i8> poison, i8 -1, i64 0), <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer)
// CHECK-NEXT: ret <vscale x 16 x i8> [[NEG]]
// CHECK-NEXT: [[NOT:%.*]] = xor <vscale x 16 x i8> [[A:%.*]], splat (i8 -1)
// CHECK-NEXT: ret <vscale x 16 x i8> [[NOT]]
//
svuint8_t neg_u8(svuint8_t a) {
return ~a;
}

// CHECK-LABEL: @neg_u16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[NEG:%.*]] = xor <vscale x 8 x i16> [[A:%.*]], shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> poison, i16 -1, i64 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer)
// CHECK-NEXT: ret <vscale x 8 x i16> [[NEG]]
// CHECK-NEXT: [[NOT:%.*]] = xor <vscale x 8 x i16> [[A:%.*]], splat (i16 -1)
// CHECK-NEXT: ret <vscale x 8 x i16> [[NOT]]
//
svuint16_t neg_u16(svuint16_t a) {
return ~a;
}

// CHECK-LABEL: @neg_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[NEG:%.*]] = xor <vscale x 4 x i32> [[A:%.*]], shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 -1, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
// CHECK-NEXT: ret <vscale x 4 x i32> [[NEG]]
// CHECK-NEXT: [[NOT:%.*]] = xor <vscale x 4 x i32> [[A:%.*]], splat (i32 -1)
// CHECK-NEXT: ret <vscale x 4 x i32> [[NOT]]
//
svuint32_t neg_u32(svuint32_t a) {
return ~a;
}

// CHECK-LABEL: @neg_u64(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[NEG:%.*]] = xor <vscale x 2 x i64> [[A:%.*]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 -1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
// CHECK-NEXT: ret <vscale x 2 x i64> [[NEG]]
// CHECK-NEXT: [[NOT:%.*]] = xor <vscale x 2 x i64> [[A:%.*]], splat (i64 -1)
// CHECK-NEXT: ret <vscale x 2 x i64> [[NOT]]
//
svuint64_t neg_u64(svuint64_t a) {
return ~a;
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8 changes: 4 additions & 4 deletions clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp
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Expand Up @@ -164,10 +164,10 @@ svint32_t cond_i32_splat(svint32_t a) {

// CHECK-LABEL: @_Z14cond_u32_splatu12__SVUint32_t(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 4 x i32> [[A:%.*]], shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 1, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 4 x i32> [[A:%.*]], splat (i32 1)
// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 4 x i32> [[CONV]], zeroinitializer
// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 4 x i1> [[VECTOR_COND]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 1, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 4 x i1> [[VECTOR_COND]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> splat (i32 1)
// CHECK-NEXT: ret <vscale x 4 x i32> [[VECTOR_SELECT]]
//
svuint32_t cond_u32_splat(svuint32_t a) {
Expand All @@ -188,10 +188,10 @@ svint64_t cond_i64_splat(svint64_t a) {

// CHECK-LABEL: @_Z14cond_u64_splatu12__SVUint64_t(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 2 x i64> [[A:%.*]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 2 x i64> [[A:%.*]], splat (i64 1)
// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 2 x i64> [[CONV]], zeroinitializer
// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 2 x i1> [[VECTOR_COND]], <vscale x 2 x i64> [[A]], <vscale x 2 x i64> shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 2 x i1> [[VECTOR_COND]], <vscale x 2 x i64> [[A]], <vscale x 2 x i64> splat (i64 1)
// CHECK-NEXT: ret <vscale x 2 x i64> [[VECTOR_SELECT]]
//
svuint64_t cond_u64_splat(svuint64_t a) {
Expand Down
18 changes: 18 additions & 0 deletions llvm/lib/IR/AsmWriter.cpp
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Expand Up @@ -1741,6 +1741,24 @@ static void WriteConstantInternal(raw_ostream &Out, const Constant *CV,
}

if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(CV)) {
// Use the same shorthand for splat vector (i.e. "splat(Ty val)") as is
// permitted on IR input to reduce the output changes when enabling
// UseConstant{Int,FP}ForScalableSplat.
// TODO: Remove this block when the UseConstant{Int,FP}ForScalableSplat
// options are removed.
if (CE->getOpcode() == Instruction::ShuffleVector) {
if (auto *SplatVal = CE->getSplatValue()) {
if (isa<ConstantInt>(SplatVal) || isa<ConstantFP>(SplatVal)) {
Out << "splat (";
WriterCtx.TypePrinter->print(SplatVal->getType(), Out);
Out << ' ';
WriteAsOperandInternal(Out, SplatVal, WriterCtx);
Out << ')';
return;
}
}
}

Out << CE->getOpcodeName();
WriteOptimizationInfo(Out, CE);
Out << " (";
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4 changes: 2 additions & 2 deletions llvm/test/Assembler/constant-splat.ll
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Expand Up @@ -51,13 +51,13 @@ define <4 x i32> @ret_fixed_lenth_vector_splat_i32() {
}

define void @add_fixed_lenth_vector_splat_double(<vscale x 2 x double> %a) {
; CHECK: %add = fadd <vscale x 2 x double> %a, shufflevector (<vscale x 2 x double> insertelement (<vscale x 2 x double> poison, double 5.700000e+00, i64 0), <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer)
; CHECK: %add = fadd <vscale x 2 x double> %a, splat (double 5.700000e+00)
%add = fadd <vscale x 2 x double> %a, splat (double 5.700000e+00)
ret void
}

define <vscale x 4 x i32> @ret_scalable_vector_splat_i32() {
; CHECK: ret <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 78, i64 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
; CHECK: ret <vscale x 4 x i32> splat (i32 78)
ret <vscale x 4 x i32> splat (i32 78)
}

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4 changes: 2 additions & 2 deletions llvm/test/Bitcode/vscale-shuffle.ll
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Expand Up @@ -2,8 +2,8 @@
; RUN: verify-uselistorder < %s

define void @f() {
%l = call <vscale x 16 x i8> @l(<vscale x 16 x i1> shufflevector (<vscale x 16 x i1> insertelement (<vscale x 16 x i1> undef, i1 true, i32 0), <vscale x 16 x i1> undef, <vscale x 16 x i32> zeroinitializer))
%i = add <vscale x 2 x i64> undef, shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 1, i32 0), <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer)
%l = call <vscale x 16 x i8> @l(<vscale x 16 x i1> splat (i1 true))
%i = add <vscale x 2 x i64> undef, splat (i64 1)
unreachable
}

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