[HLSL] Implement elementwise firstbitlow builtin #116858
There are no files selected for viewing
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
|
|
@@ -108,8 +108,8 @@ class SPIRVInstructionSelector : public InstructionSelector { | |
| unsigned Opcode) const; | ||
|
|
||
| bool selectFirstBitSet64(Register ResVReg, const SPIRVType *ResType, | ||
| MachineInstr &I, Register SrcReg, | ||
| unsigned BitSetOpcode, bool SwapPrimarySide) const; | ||
|
|
||
| bool selectGlobalValue(Register ResVReg, MachineInstr &I, | ||
| const MachineInstr *Init = nullptr) const; | ||
|
|
@@ -3171,23 +3171,116 @@ bool SPIRVInstructionSelector::selectFirstBitSet32(Register ResVReg, | |
| .constrainAllUses(TII, TRI, RBI); | ||
| } | ||
|
|
||
| bool SPIRVInstructionSelector::selectFirstBitSet64( | ||
| Register ResVReg, const SPIRVType *ResType, MachineInstr &I, | ||
| Register SrcReg, unsigned BitSetOpcode, bool SwapPrimarySide) const { | ||
| unsigned ComponentCount = GR.getScalarOrVectorComponentCount(ResType); | ||
| SPIRVType *BaseType = GR.retrieveScalarOrVectorIntType(ResType); | ||
| bool ZeroAsNull = STI.isOpenCLEnv(); | ||
| Register ConstIntZero = | ||
| GR.getOrCreateConstInt(0, I, BaseType, TII, ZeroAsNull); | ||
| Register ConstIntOne = | ||
| GR.getOrCreateConstInt(1, I, BaseType, TII, ZeroAsNull); | ||
|
|
||
| // SPIRV doesn't support vectors with more than 4 components. Since the | ||
| // algoritm below converts i64 -> i32x2 and i64x4 -> i32x8 it can only | ||
| // operate on vectors with 2 or less components. When largers vectors are | ||
| // seen. Split them, recurse, then recombine them. | ||
V-FEXrt marked this conversation as resolved.
Show resolved
Hide resolved
|
||
| if (ComponentCount > 2) { | ||
| unsigned LeftComponentCount = ComponentCount / 2; | ||
|
There was a problem hiding this comment. Will this code be affected if vectors of size greater than 4 are supported in hlsl in the future? This might be a question for someone besides @V-FEXrt There was a problem hiding this comment. I tried to write it to handle that case. It should just keep recursing and splitting the vectors in half until its under 2 components. I do think we are strictly limited by SPIRV here though. Say hlsl supported u64x8, we still have to accept the vec8 in as a parameter and return a vec8 out. Both of which would require invalid SPIRV There was a problem hiding this comment. Actually one thing I was considering was to just explicitly handle the vec3 and vec4 cases then assert for anything higher but they are equally as messy while being strictly less general There was a problem hiding this comment. I think/wonder if its possible that a previous part of the code will force the vectors to be vec4 or smaller, but I'm unsure. There was a problem hiding this comment.
I don't think this code can validly handle vectors that are > vec4 because the splitting action will create vectors which are too large in some cases. There was a problem hiding this comment. Can you give an example? I'm pretty sure the splitting will never create a vector too large (but the merging back together certainly can) Example: Given selectFirstBitSet64(u64x12); // Top
selectFirstBitSet64Overflow(u64x12); // Top
selectFirstBitSet64(u64x6); // Top.Left
selectFirstBitSet64Overflow(u64x6); // Top.Left
selectFirstBitSet64(u64x3); // Top.Left.Left
selectFirstBitSet64Overflow(u64x3); // Top.Left.Left
selectFirstBitSet64(u64); // Top.Left.Left.Left
selectFirstBitSet64(u64x2); // Top.Left.Left.Right
selectFirstBitSet64Overflow(u64x3); // Top.Left.Right
selectFirstBitSet64(u64); // Top.Left.Right.Left
selectFirstBitSet64(u64x2); // Top.Left.Right.Right
selectFirstBitSet64Overflow(u64x6); // Top.Right
selectFirstBitSet64(u64x3); // Top.Right.Left
selectFirstBitSet64Overflow(u64x3); // Top.Right.Left
selectFirstBitSet64(u64); // Top.Right.Left.Left
selectFirstBitSet64(u64x2); // Top.Right.Left.Right
selectFirstBitSet64Overflow(u64x3); // Top.Right.Right
selectFirstBitSet64(u64); // Top.Right.Right.Left
selectFirstBitSet64(u64x2); // Top.Right.Right.RightThere was a problem hiding this comment. When you split a size 12 vector for the potential recursive call, you create two intermediate registers which contain vectors of size 6. I think you can see this in your callstack actually. There was a problem hiding this comment. Ah yep. :/ I was hoping it was clean and only Probably just go with the assert that its never larger than |
||
| unsigned RightComponentCount = ComponentCount - LeftComponentCount; | ||
| bool LeftIsVector = LeftComponentCount > 1; | ||
|
|
||
| // Split the SrcReg in half into 2 smaller vec registers | ||
| // (ie i64x4 -> i64x2, i64x2) | ||
| MachineIRBuilder MIRBuilder(I); | ||
| SPIRVType *OpType = GR.getOrCreateSPIRVIntegerType(64, MIRBuilder); | ||
| SPIRVType *LeftVecOpType; | ||
V-FEXrt marked this conversation as resolved.
Show resolved
Hide resolved
|
||
| SPIRVType *LeftVecResType; | ||
| if (LeftIsVector) { | ||
| LeftVecOpType = | ||
| GR.getOrCreateSPIRVVectorType(OpType, LeftComponentCount, MIRBuilder); | ||
| LeftVecResType = GR.getOrCreateSPIRVVectorType( | ||
| BaseType, LeftComponentCount, MIRBuilder); | ||
| } else { | ||
| LeftVecOpType = OpType; | ||
| LeftVecResType = BaseType; | ||
| } | ||
|
|
||
| SPIRVType *RightVecOpType = | ||
| GR.getOrCreateSPIRVVectorType(OpType, RightComponentCount, MIRBuilder); | ||
| SPIRVType *RightVecResType = GR.getOrCreateSPIRVVectorType( | ||
| BaseType, RightComponentCount, MIRBuilder); | ||
|
|
||
| Register LeftSideIn = | ||
| MRI->createVirtualRegister(GR.getRegClass(LeftVecOpType)); | ||
| Register RightSideIn = | ||
| MRI->createVirtualRegister(GR.getRegClass(RightVecOpType)); | ||
|
|
||
| bool Result; | ||
|
|
||
| if (LeftIsVector) { | ||
| auto MIB = | ||
V-FEXrt marked this conversation as resolved.
Show resolved
Hide resolved
|
||
| BuildMI(*I.getParent(), I, I.getDebugLoc(), | ||
| TII.get(SPIRV::OpVectorShuffle)) | ||
| .addDef(LeftSideIn) | ||
| .addUse(GR.getSPIRVTypeID(LeftVecOpType)) | ||
| .addUse(SrcReg) | ||
| // Per the spec, repeat the vector if only one vec is needed | ||
| .addUse(SrcReg); | ||
|
|
||
| for (unsigned J = 0; J < LeftComponentCount; J++) { | ||
| MIB.addImm(J); | ||
| } | ||
|
|
||
| Result = MIB.constrainAllUses(TII, TRI, RBI); | ||
| } else { | ||
| Result = | ||
| selectOpWithSrcs(LeftSideIn, LeftVecOpType, I, {SrcReg, ConstIntZero}, | ||
| SPIRV::OpVectorExtractDynamic); | ||
| } | ||
|
|
||
| auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), | ||
| TII.get(SPIRV::OpVectorShuffle)) | ||
| .addDef(RightSideIn) | ||
| .addUse(GR.getSPIRVTypeID(RightVecOpType)) | ||
| .addUse(SrcReg) | ||
| // Per the spec, repeat the vector if only one vec is needed | ||
| .addUse(SrcReg); | ||
|
|
||
| for (unsigned J = LeftComponentCount; J < ComponentCount; J++) { | ||
| MIB.addImm(J); | ||
| } | ||
|
|
||
| Result = Result && MIB.constrainAllUses(TII, TRI, RBI); | ||
|
|
||
| // Recursively call selectFirstBitSet64 on the 2 registers | ||
| Register LeftSideOut = | ||
| MRI->createVirtualRegister(GR.getRegClass(LeftVecResType)); | ||
| Register RightSideOut = | ||
| MRI->createVirtualRegister(GR.getRegClass(RightVecResType)); | ||
| Result = Result && | ||
| selectFirstBitSet64(LeftSideOut, LeftVecResType, I, LeftSideIn, | ||
| BitSetOpcode, SwapPrimarySide); | ||
| Result = Result && | ||
| selectFirstBitSet64(RightSideOut, RightVecResType, I, RightSideIn, | ||
| BitSetOpcode, SwapPrimarySide); | ||
|
|
||
| // Join the two resulting registers back into the return type | ||
| // (ie i32x2, i32x2 -> i32x4) | ||
| return Result && | ||
| selectOpWithSrcs(ResVReg, ResType, I, {LeftSideOut, RightSideOut}, | ||
| SPIRV::OpCompositeConstruct); | ||
| } | ||
|
|
||
| // 1. Split int64 into 2 pieces using a bitcast | ||
V-FEXrt marked this conversation as resolved.
Show resolved
Hide resolved
|
||
| MachineIRBuilder MIRBuilder(I); | ||
| SPIRVType *PostCastType = | ||
| GR.getOrCreateSPIRVVectorType(BaseType, 2 * ComponentCount, MIRBuilder); | ||
V-FEXrt marked this conversation as resolved.
Show resolved
Hide resolved
|
||
| Register BitcastReg = | ||
| MRI->createVirtualRegister(GR.getRegClass(PostCastType)); | ||
| bool Result = | ||
| selectOpWithSrcs(BitcastReg, PostCastType, I, {SrcReg}, SPIRV::OpBitcast); | ||
|
|
||
| // 2. Find the first set bit from the primary side for all the pieces in #1 | ||
| Register FBSReg = MRI->createVirtualRegister(GR.getRegClass(PostCastType)); | ||
|
|
@@ -3198,20 +3291,15 @@ bool SPIRVInstructionSelector::selectFirstBitSet64(Register ResVReg, | |
| Register HighReg = MRI->createVirtualRegister(GR.getRegClass(ResType)); | ||
| Register LowReg = MRI->createVirtualRegister(GR.getRegClass(ResType)); | ||
|
|
||
| bool IsScalarRes = ResType->getOpcode() != SPIRV::OpTypeVector; | ||
| if (IsScalarRes) { | ||
| // if scalar do a vector extract | ||
| Result = | ||
| Result && selectOpWithSrcs(HighReg, ResType, I, {FBSReg, ConstIntZero}, | ||
| SPIRV::OpVectorExtractDynamic); | ||
| Result = | ||
| Result && selectOpWithSrcs(LowReg, ResType, I, {FBSReg, ConstIntOne}, | ||
| SPIRV::OpVectorExtractDynamic); | ||
| } else { | ||
| // if vector do a shufflevector | ||
| auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), | ||
|
|
@@ -3324,7 +3412,7 @@ bool SPIRVInstructionSelector::selectFirstBitHigh(Register ResVReg, | |
| case 32: | ||
| return selectFirstBitSet32(ResVReg, ResType, I, OpReg, BitSetOpcode); | ||
| case 64: | ||
| return selectFirstBitSet64(ResVReg, ResType, I, OpReg, BitSetOpcode, | ||
| /*SwapPrimarySide=*/false); | ||
| default: | ||
| report_fatal_error( | ||
|
|
@@ -3350,7 +3438,7 @@ bool SPIRVInstructionSelector::selectFirstBitLow(Register ResVReg, | |
| case 32: | ||
| return selectFirstBitSet32(ResVReg, ResType, I, OpReg, BitSetOpcode); | ||
| case 64: | ||
| return selectFirstBitSet64(ResVReg, ResType, I, OpReg, BitSetOpcode, | ||
| /*SwapPrimarySide=*/true); | ||
| default: | ||
| report_fatal_error("spv_firstbitlow only supports 16,32,64 bits."); | ||
|
|
||
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Oops, something went wrong.
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Uh oh!
There was an error while loading. Please reload this page.