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[AArch64] Don't emit Neon in streaming[-compatible] functions with -fzero-call-used-regs #116995

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Merged
merged 2 commits into from
Nov 21, 2024
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[AArch64] Don't emit Neon in streaming[-compatible] functions with -fzero-call-used-regs #116995

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[AArch64] Don't emit Neon in streaming[-compatible] functions with -f…
MacDue Nov 20, 2024
61bd704
Add const back
MacDue Nov 20, 2024
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1010,7 +1010,7 @@ void AArch64FrameLowering::emitZeroCallUsedRegs(BitVector RegsToZero,

BitVector GPRsToZero(TRI.getNumRegs());
BitVector FPRsToZero(TRI.getNumRegs());
bool HasSVE = STI.hasSVE();
bool HasSVE = STI.isSVEorStreamingSVEAvailable();
for (MCRegister Reg : RegsToZero.set_bits()) {
if (TRI.isGeneralPurposeRegister(MF, Reg)) {
// For GPRs, we only care to clear out the 64-bit register.
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13 changes: 10 additions & 3 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
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Expand Up @@ -9694,19 +9694,26 @@ void AArch64InstrInfo::buildClearRegister(Register Reg, MachineBasicBlock &MBB,
MachineBasicBlock::iterator Iter,
DebugLoc &DL,
bool AllowSideEffects) const {
const MachineFunction &MF = *MBB.getParent();
MachineFunction &MF = *MBB.getParent();
const AArch64Subtarget &STI = MF.getSubtarget<AArch64Subtarget>();
const AArch64RegisterInfo &TRI = *STI.getRegisterInfo();

if (TRI.isGeneralPurposeRegister(MF, Reg)) {
BuildMI(MBB, Iter, DL, get(AArch64::MOVZXi), Reg).addImm(0).addImm(0);
} else if (STI.hasSVE()) {
} else if (STI.isSVEorStreamingSVEAvailable()) {
BuildMI(MBB, Iter, DL, get(AArch64::DUP_ZI_D), Reg)
.addImm(0)
.addImm(0);
} else {
} else if (STI.isNeonAvailable()) {
BuildMI(MBB, Iter, DL, get(AArch64::MOVIv2d_ns), Reg)
.addImm(0);
} else {
// This is a streaming-compatible function without SVE. We don't have full
// Neon (just FPRs), so we can at most use the first 64-bit sub-register.
// So given `movi v..` would be illegal use `fmov d..` instead.
Comment on lines +9711 to +9713
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@MacDue MacDue Nov 20, 2024

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I'm pretty sure this is correct. I don't think there's a way to zero the full 128 bits without Neon or SVE in a streaming-compatible function (we at most have the D registers).

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@davemgreen davemgreen Nov 20, 2024

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fmovd (and all other instructions that set a d register) will implicitly zero the upper bits of the register too, so it should be OK even if other parts of the register do get used.

assert(STI.hasNEON() && "Expected to have NEON.");
Register Reg64 = TRI.getSubReg(Reg, AArch64::dsub);
BuildMI(MBB, Iter, DL, get(AArch64::FMOVD0), Reg64);
}
}

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