[hexagon] Add support for llvm.debugtrap #117049

androm3da · 2024-11-20T20:59:21Z

Also: set hasSideEffects on Y2_break instruction.

Also: set `hasSideEffects` on `Y2_break` instruction.

llvmbot · 2024-11-20T20:59:58Z

@llvm/pr-subscribers-backend-hexagon

Author: Brian Cain (androm3da)

Changes

Also: set hasSideEffects on Y2_break instruction.

Full diff: https://github.com/llvm/llvm-project/pull/117049.diff

4 Files Affected:

(modified) llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td (+1)
(modified) llvm/lib/Target/Hexagon/HexagonISelLowering.cpp (+2-1)
(modified) llvm/lib/Target/Hexagon/HexagonPatterns.td (+1)
(modified) llvm/test/CodeGen/Hexagon/trap-crash.ll (+12-7)

diff --git a/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
index 0351217f441df2..7935c4b86af535 100644
--- a/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
+++ b/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
@@ -40411,6 +40411,7 @@ def Y2_break : HInst<
 tc_55255f2b, TypeCR>, Enc_e3b0c4 {
 let Inst{13-0} = 0b00000000000000;
 let Inst{31-16} = 0b0110110000100000;
+let hasSideEffects = 1;
 let isSolo = 1;
 }
 def Y2_ciad : HInst<
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 08a9c95ee7359f..77d8494921773b 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -1498,7 +1498,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
   // All operations default to "legal", except:
   // - indexed loads and stores (pre-/post-incremented),
   // - ANY_EXTEND_VECTOR_INREG, ATOMIC_CMP_SWAP_WITH_SUCCESS, CONCAT_VECTORS,
-  //   ConstantFP, DEBUGTRAP, FCEIL, FCOPYSIGN, FEXP, FEXP2, FFLOOR, FGETSIGN,
+  //   ConstantFP, FCEIL, FCOPYSIGN, FEXP, FEXP2, FFLOOR, FGETSIGN,
   //   FLOG, FLOG2, FLOG10, FMAXNUM, FMINNUM, FNEARBYINT, FRINT, FROUND, TRAP,
   //   FTRUNC, PREFETCH, SIGN_EXTEND_VECTOR_INREG, ZERO_EXTEND_VECTOR_INREG,
   // which default to "expand" for at least one type.
@@ -1507,6 +1507,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::ConstantFP,           MVT::f32,   Legal);
   setOperationAction(ISD::ConstantFP,           MVT::f64,   Legal);
   setOperationAction(ISD::TRAP,                 MVT::Other, Legal);
+  setOperationAction(ISD::DEBUGTRAP,            MVT::Other, Legal);
   setOperationAction(ISD::ConstantPool,         MVT::i32,   Custom);
   setOperationAction(ISD::JumpTable,            MVT::i32,   Custom);
   setOperationAction(ISD::BUILD_PAIR,           MVT::i64,   Expand);
diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td
index baa552fcd220d8..fa6d4c6058f217 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatterns.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td
@@ -3384,6 +3384,7 @@ def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>;
 def: Pat<(HexagonBARRIER), (Y2_barrier)>;
 
 def: Pat<(trap), (PS_crash)>;
+def: Pat<(debugtrap), (Y2_break)>;
 
 // Read cycle counter.
 def SDTInt64Leaf: SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>;
diff --git a/llvm/test/CodeGen/Hexagon/trap-crash.ll b/llvm/test/CodeGen/Hexagon/trap-crash.ll
index e940d98b620c57..a0afe5fdd30414 100644
--- a/llvm/test/CodeGen/Hexagon/trap-crash.ll
+++ b/llvm/test/CodeGen/Hexagon/trap-crash.ll
@@ -1,20 +1,25 @@
-; RUN: llc -march=hexagon < %s | FileCheck %s
+; RUN: llc -march=hexagon --verify-machineinstrs < %s | FileCheck %s
 
 ; Generate code that is guaranteed to crash. At the moment, it's a
 ; misaligned load.
+; CHECK-LABEL: f0
 ; CHECK: memd(##3134984174)
 
 target triple = "hexagon"
 
-; Function Attrs: noreturn nounwind
-define i32 @f0() #0 {
+define i32 @f0() noreturn nounwind  {
 entry:
   tail call void @llvm.trap()
   unreachable
 }
 
-; Function Attrs: cold noreturn nounwind
-declare void @llvm.trap() #1
+; CHECK-LABEL: f1
+; CHECK: brkpt
+define i32 @f1() noreturn nounwind {
+entry:
+  tail call void @llvm.debugtrap()
+  unreachable
+}
 
-attributes #0 = { noreturn nounwind "target-cpu"="hexagonv60" }
-attributes #1 = { cold noreturn nounwind }
+declare void @llvm.trap() nounwind
+declare void @llvm.debugtrap() nounwind

github-actions · 2024-11-20T21:02:44Z

⚠️ C/C++ code formatter, clang-format found issues in your code. ⚠️

You can test this locally with the following command:

git-clang-format --diff 3282be1f8d278836135cc1bda130abb031155701 9dbcb9632f55f32fd51153a97ca113d221377c83 --extensions cpp -- llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

View the diff from clang-format here.

diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 77d8494921..1f7f0bf0ac 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -1507,7 +1507,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::ConstantFP,           MVT::f32,   Legal);
   setOperationAction(ISD::ConstantFP,           MVT::f64,   Legal);
   setOperationAction(ISD::TRAP,                 MVT::Other, Legal);
-  setOperationAction(ISD::DEBUGTRAP,            MVT::Other, Legal);
+  setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
   setOperationAction(ISD::ConstantPool,         MVT::i32,   Custom);
   setOperationAction(ISD::JumpTable,            MVT::i32,   Custom);
   setOperationAction(ISD::BUILD_PAIR,           MVT::i64,   Expand);

androm3da · 2024-11-20T21:10:53Z

⚠️ C/C++ code formatter, clang-format found issues in your code. ⚠️

You can test this locally with the following command:

git-clang-format --diff 3282be1f8d278836135cc1bda130abb031155701 9dbcb9632f55f32fd51153a97ca113d221377c83 --extensions cpp -- llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

View the diff from clang-format here.

diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 77d8494921..1f7f0bf0ac 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -1507,7 +1507,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::ConstantFP,           MVT::f32,   Legal);
   setOperationAction(ISD::ConstantFP,           MVT::f64,   Legal);
   setOperationAction(ISD::TRAP,                 MVT::Other, Legal);
-  setOperationAction(ISD::DEBUGTRAP,            MVT::Other, Legal);
+  setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
   setOperationAction(ISD::ConstantPool,         MVT::i32,   Custom);
   setOperationAction(ISD::JumpTable,            MVT::i32,   Custom);
   setOperationAction(ISD::BUILD_PAIR,           MVT::i64,   Expand);

I overrode clang-format deliberately in order to match the surrounding code.

androm3da · 2024-12-03T16:09:03Z

ping @iajbar @SundeepKushwaha

llvm-ci · 2024-12-04T18:18:15Z

LLVM Buildbot has detected a new failure on builder flang-aarch64-out-of-tree running on linaro-flang-aarch64-out-of-tree while building llvm at step 8 "test-build-flang-unified-tree-check-flang".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/53/builds/8954

Here is the relevant piece of the build log for the reference

Step 8 (test-build-flang-unified-tree-check-flang) failure: test (failure)
******************** TEST 'Flang :: Fir/CUDA/cuda-target-rewrite.mlir' FAILED ********************
Exit Code: 1

Command Output (stderr):
--
RUN: at line 1: fir-opt --target-rewrite /home/tcwg-buildbot/worker/flang-aarch64-out-of-tree/llvm-project/flang/test/Fir/CUDA/cuda-target-rewrite.mlir | /home/tcwg-buildbot/worker/flang-aarch64-out-of-tree/build_llvm/bin/FileCheck /home/tcwg-buildbot/worker/flang-aarch64-out-of-tree/llvm-project/flang/test/Fir/CUDA/cuda-target-rewrite.mlir
+ fir-opt --target-rewrite /home/tcwg-buildbot/worker/flang-aarch64-out-of-tree/llvm-project/flang/test/Fir/CUDA/cuda-target-rewrite.mlir
+ /home/tcwg-buildbot/worker/flang-aarch64-out-of-tree/build_llvm/bin/FileCheck /home/tcwg-buildbot/worker/flang-aarch64-out-of-tree/llvm-project/flang/test/Fir/CUDA/cuda-target-rewrite.mlir
/home/tcwg-buildbot/worker/flang-aarch64-out-of-tree/llvm-project/flang/test/Fir/CUDA/cuda-target-rewrite.mlir:15:11: error: CHECK: expected string not found in input
// CHECK: %{{.*}} = fir.call @_FortranAzpowk(%{{.*}}, %{{.*}}, %{{.*}}) : (f64, f64, i64) -> tuple<f64, f64>
          ^
<stdin>:3:22: note: scanning from here
 gpu.func @_QPvcpowdk(%arg0: !fir.ref<complex<f64>> {cuf.data_attr = #cuf.cuda<device>, fir.bindc_name = "a"}) attributes {cuf.proc_attr = #cuf.cuda_proc<global>} {
                     ^
<stdin>:12:2: note: possible intended match here
 %7 = fir.call @_FortranAzpowk(%6, %1) : (!fir.array<2xf64>, i64) -> tuple<f64, f64>
 ^

Input file: <stdin>
Check file: /home/tcwg-buildbot/worker/flang-aarch64-out-of-tree/llvm-project/flang/test/Fir/CUDA/cuda-target-rewrite.mlir

-dump-input=help explains the following input dump.

Input was:
<<<<<<
            1: module attributes {dlti.dl_spec = #dlti.dl_spec<i64 = dense<[32, 64]> : vector<2xi64>, f128 = dense<128> : vector<2xi64>, f64 = dense<64> : vector<2xi64>, f16 = dense<16> : vector<2xi64>, i32 = dense<32> : vector<2xi64>, i16 = dense<16> : vector<2xi64>, i1 = dense<8> : vector<2xi64>, i8 = dense<8> : vector<2xi64>, !llvm.ptr = dense<64> : vector<4xi64>, "dlti.endianness" = "little">, llvm.data_layout = ""} { 
            2:  gpu.module @testmod { 
            3:  gpu.func @_QPvcpowdk(%arg0: !fir.ref<complex<f64>> {cuf.data_attr = #cuf.cuda<device>, fir.bindc_name = "a"}) attributes {cuf.proc_attr = #cuf.cuda_proc<global>} { 
check:15'0                          X~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ error: no match found
            4:  %0 = fir.alloca i64 
check:15'0     ~~~~~~~~~~~~~~~~~~~~~
            5:  %1 = fir.load %0 : !fir.ref<i64> 
check:15'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
            6:  %2 = fir.load %arg0 : !fir.ref<complex<f64>> 
check:15'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
            7:  %3 = llvm.intr.stacksave : !llvm.ptr 
check:15'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
            8:  %4 = fir.alloca !fir.array<2xf64> 
check:15'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
            9:  %5 = fir.convert %4 : (!fir.ref<!fir.array<2xf64>>) -> !fir.ref<complex<f64>> 
check:15'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           10:  fir.store %2 to %5 : !fir.ref<complex<f64>> 
check:15'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           11:  %6 = fir.load %4 : !fir.ref<!fir.array<2xf64>> 
check:15'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           12:  %7 = fir.call @_FortranAzpowk(%6, %1) : (!fir.array<2xf64>, i64) -> tuple<f64, f64> 
check:15'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
check:15'1      ?                                                                                    possible intended match
           13:  %8 = fir.alloca tuple<f64, f64> 
check:15'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
...

[hexagon] Add support for llvm.debugtrap

9dbcb96

Also: set `hasSideEffects` on `Y2_break` instruction.

androm3da requested review from SundeepKushwaha, iajbar and tedwoodward November 20, 2024 20:59

androm3da self-assigned this Nov 20, 2024

llvmbot added the backend:Hexagon label Nov 20, 2024

iajbar approved these changes Dec 3, 2024

View reviewed changes

androm3da merged commit 7748492 into llvm:main Dec 4, 2024
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