[Xtensa] Implement vararg support.

llvm/lib/Target/Xtensa/XtensaISelLowering.cpp

@@ -335,8 +335,8 @@ SDValue XtensaTargetLowering::LowerFormalArguments(
 
       // Transform the arguments stored on
       // physical registers into virtual ones
-      unsigned Register = MF.addLiveIn(VA.getLocReg(), &Xtensa::ARRegClass);
-      SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Register, RegVT);
+      Register Reg = MF.addLiveIn(VA.getLocReg(), &Xtensa::ARRegClass);
+      SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
 
       // If this is an 8 or 16-bit value, it has been passed promoted
       // to 32 bits.  Insert an assert[sz]ext to capture this, then
@@ -382,8 +382,8 @@ SDValue XtensaTargetLowering::LowerFormalArguments(
   }
 
   if (IsVarArg) {
-    ArrayRef<MCPhysReg> ArgRegs = ArrayRef(IntRegs);
-    unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
+    unsigned Idx = CCInfo.getFirstUnallocated(IntRegs);
+    unsigned ArgRegsNum = std::size(IntRegs);
     const TargetRegisterClass *RC = &Xtensa::ARRegClass;
     MachineFrameInfo &MFI = MF.getFrameInfo();
     MachineRegisterInfo &RegInfo = MF.getRegInfo();
@@ -402,11 +402,11 @@ SDValue XtensaTargetLowering::LowerFormalArguments(
 
     // If all registers are allocated, then all varargs must be passed on the
     // stack and we don't need to save any argregs.
-    if (ArgRegs.size() == Idx) {
+    if (ArgRegsNum == Idx) {
       VaArgOffset = CCInfo.getStackSize();
       VarArgsSaveSize = 0;
     } else {
-      VarArgsSaveSize = RegSize * (ArgRegs.size() - Idx);
+      VarArgsSaveSize = RegSize * (ArgRegsNum - Idx);
       VaArgOffset = -VarArgsSaveSize;
 
       // Record the frame index of the first variable argument
@@ -416,9 +416,9 @@ SDValue XtensaTargetLowering::LowerFormalArguments(
 
       // Copy the integer registers that may have been used for passing varargs
       // to the vararg save area.
-      for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += RegSize) {
+      for (unsigned I = Idx; I < ArgRegsNum; ++I, VaArgOffset += RegSize) {
         const Register Reg = RegInfo.createVirtualRegister(RC);
-        RegInfo.addLiveIn(ArgRegs[I], Reg);
+        RegInfo.addLiveIn(IntRegs[I], Reg);
 
         SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
         FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true);

llvm/lib/Target/Xtensa/XtensaMachineFunctionInfo.h

@@ -25,13 +25,14 @@ class XtensaMachineFunctionInfo : public MachineFunctionInfo {
   /// FrameIndex of the spill slot for the scratch register in BranchRelaxation.
   int BranchRelaxationScratchFrameIndex = -1;
   unsigned VarArgsFirstGPR;
-  int VarArgsStackOffset;
-  unsigned VarArgsFrameIndex;
+  unsigned VarArgsOnStackFrameIndex;
+  unsigned VarArgsInRegsFrameIndex;
 
 public:
   explicit XtensaMachineFunctionInfo(const Function &F,
                                      const TargetSubtargetInfo *STI)
-      : VarArgsFirstGPR(0), VarArgsStackOffset(0), VarArgsFrameIndex(0) {}
+      : VarArgsFirstGPR(0), VarArgsOnStackFrameIndex(0),
+        VarArgsInRegsFrameIndex(0) {}
 
   int getBranchRelaxationScratchFrameIndex() const {
     return BranchRelaxationScratchFrameIndex;
@@ -43,12 +44,18 @@ class XtensaMachineFunctionInfo : public MachineFunctionInfo {
   unsigned getVarArgsFirstGPR() const { return VarArgsFirstGPR; }
   void setVarArgsFirstGPR(unsigned GPR) { VarArgsFirstGPR = GPR; }
 
-  int getVarArgsOnStackFrameIndex() const { return VarArgsStackOffset; }
-  void setVarArgsOnStackFrameIndex(int Offset) { VarArgsStackOffset = Offset; }
+  unsigned getVarArgsOnStackFrameIndex() const {
+    return VarArgsOnStackFrameIndex;
+  }
+  void setVarArgsOnStackFrameIndex(unsigned FI) {
+    VarArgsOnStackFrameIndex = FI;
+  }
 
   // Get and set the frame index of the first stack vararg.
-  unsigned getVarArgsInRegsFrameIndex() const { return VarArgsFrameIndex; }
-  void setVarArgsInRegsFrameIndex(unsigned FI) { VarArgsFrameIndex = FI; }
+  unsigned getVarArgsInRegsFrameIndex() const {
+    return VarArgsInRegsFrameIndex;
+  }
+  void setVarArgsInRegsFrameIndex(unsigned FI) { VarArgsInRegsFrameIndex = FI; }
 };
 
 } // namespace llvm